DS3173N datasheet(31/232 Pages) DALLAS

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PIN NAME

TYPE

PIN DESCRIPTION

This signal can be inverted.

ROHSOFn

Receive Overhead Start Of Frame

ROHSOFn: When the port framer is configured for one of the DS3 or E3 framing

modes this signal is used to mark the start of a DS3 or E3 overhead sequence on the

ROHn pins. In T3 mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the

FAS word is marked. In G.832 E3 mode, the first bit of the FA1 byte is marked. The

sequence starts on the same high to low transition of the ROHCLKn clock that this

signal is high. This signal is updated at the same time as the ROHCLKn signal

transitions high to low.

This signal can be inverted.

DS3/E3 Serial Data Overhead Interface

TCLKIn

Transmit Line Clock Input

TCLKIn: This clock is typically used for the reference clock for the TSOFIn, TSERn,

and TSOFOn / TDENn signals but can also be used as the reference for the TPOSn /

TDATn and TNEGn signals. This clock is not used when the part is in loop time mode

or the CLAD clocks are used as the transmit clock source. (PORT.CR3.CLADC)

This input signal can be inverted.

DS3: 44.736 MHz +20 ppm

E3: 34.368 MHz +20 ppm

TSOFIn

Transmit Start Of Frame Input

See Table 10-20.

TSOFIn: This signal can be used to align the start of the DS3 or E3 frames on the

TSERn pin to an external signal. In SCT modes, the TSOFIn signal can be used to

align the start of frame signal position on the TSERn/TOHn

Pin to the rising edge of a signal on this pin. The signal edge does not need to occur

on every frame and can be tied high or low. The signal is sampled on the positive

clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise

it is sampled on the falling edge of the clock. The signal is typically referenced to the

TCLKIn transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn,

RCLKOn and RLCLKn clock pins.

This signal can be inverted.

TSERn

Transmit Serial Data

TSERn: When the port framer is configured for either the DS3 or E3 SCT modes, this

pin is used as the source of the DS3/E3 payload data. When the port is configured for

a clear channel mode, this pin is used as the source of the DS3/E3 data signal. The

signal is sampled on the positive clock edge of the referenced clock pin if the clock

pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. The

signal is typically referenced to the TCLKIn transmit clock input pins, but it can be

referenced to the TLCLKn, TCLKOn / TGCLKn, RCLKOn and RLCLKn clock pins

This signal can be inverted.

DS3: 44.736 Mbps +20ppm

E3: 34.368 Mbps +20ppm

TCLKOn /

TGCLKn

Transmit Clock Output / Gapped Clock

See Table 10-22.

TCLKOn: When the port is configured for unframed SCT or framed SCT modes and

TCLKOn is selected, this clock output is enabled. This clock is the same clock as the

internal framer transmit clock. This clock is typically used for the reference clock for

the TSOFIn, TSERn, and TSOFOn / TDENn signals but can also be used as the

reference for the TPOSn / TDATn and TNEGn signals.

This signal can be inverted.

DS3: 44.736 MHz +20 ppm

E3: 34.368 MHz +20 ppm

TGCLKn: When the port is configured for framed DS3/E3 mode and TGCLKn is

selected, this gated output clock is enabled. This gapped clock is the same clock as

the internal framer transmit clock and is gated by TDENn. This clock is typically used

DS3173N Datasheet(PDF) 31 Page - Dallas Semiconductor

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