DS3173N datasheet(95/232 Pages) DALLAS

95 / 232 page

DS3171/DS3172/DS3173/DS3174

95 of 231

Table 10-30. Payload Label Match Status

EXPECTED

RECEIVED

STATUS

000

Match

000

001

Mismatch

000

XXX

Mismatch

001

000

Mismatch

001

Match

001

XXX

Match

XXX

000

Mismatch

XXX

001

Match

XXX

Match

XXX

YYY

Mismatch

XXX and YYY equal any value other than 000 or 001; XXX

¹ YYY

The multiframe indicator and timing marker bits (sixth, seventh, and eighth bits of the MA byte) can be integrated

and stored in three register bits or extracted, integrated, and stored in four register bits. The bits (three or four) are

stored with a change indication. The multiframe indicator and timing marker storage type is programmable

(integrated or extracted). When the multiframe indicator and timing marker bits are integrated, the last three bits of

the MA byte are integrated and stored in three register bits. When the multiframe indicator and timing marker bits

are extracted, four timing source indicator bits are transferred in a four-frame multiframe, MSB first. The multiframe

indicator bits (sixth and seventh bits of the MA byte) identify the phase of the multiframe (00, 01, 10, or 11). The

timing marker bit (eighth bit of the MA byte) contains the timing source indicator bit indicated by the multiframe

indicator bits (first, second, third, or fourth bit respectively). The four timing source indicator bits are extracted from

the multiframe, integrated, and stored in four register bits with unstable and change indications.

The NR byte is integrated and stored in a register along with a change indication, it is sent to the receive FEAC

controller, and it can be sent to the receive HDLC controller. The byte sent to the receive HDLC controller is

programmable (NR or GC).

The GC byte is integrated and stored in a register along with a change indication, and can be sent to the receive

HDLC controller. The byte sent to the receive HDLC controller is programmable (NR or GC).

10.6.8.10 Receive G.832 Downstream AIS Generation

Downstream G.832 E3 AIS can be automatically generated on an OOF, LOS, or AIS condition or manually

inserted. If automatic downstream AIS is enabled, downstream AIS is inserted when an LOS, OOF, or AIS

condition is declared. Automatic downstream AIS is programmable (on or off). If manual downstream AIS insertion

is enabled, downstream AIS is inserted. Manual downstream AIS insertion is programmable (on or off).

Downstream AIS is removed when all OOF, LOS, and AIS conditions are terminated and manual downstream AIS

insertion is disabled. RPDT will be forced to all ones during downstream AIS.

10.7 HDLC Overhead Controller

10.7.1 General Description

The DS3174,3,2,1 devices contain built-in HDLC controllers (one per port) with 256 byte FIFOs for

insertion/extraction of DS3 PMDL, G.751 Sn bit and G.832 NR/GC bytes.

The HDLC Overhead Controller demaps HDLC overhead packets from the DS3/E3 data stream in the receive

direction and maps HDLC packets into the DS3/E3 data stream in the transmit direction.

DS3173N Datasheet(PDF) 95 Page - Dallas Semiconductor

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