DS3173N datasheet(62/232 Pages) DALLAS

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Table 10-10. Reset and Power-Down Sources

Forced: Internally controlled

Set: User controlled

INTERNAL SIGNALS

The reset signals in the device are asynchronous so they no not require a clock to put the logic into the reset state.

Clock signals may be needed to make the logic come out of the reset state.

The power-down function disables the appropriate clocks to cause the logic to generate a minimum of power. It

also puts the LIU circuits into the power-down mode. The 8KREF and ONESEC circuits can be powered down by

disabling the 8KREF source. The CLAD can also be powered down by disabling it.

After a global reset, all of the control and status registers in all ports are set to their default values and all the other

flops are reset to their reset values. The global register GL.CR1.RSTDP, and the port register PORT.CR1.RSTDP

and PORT.CR1.PD bits in all ports, are set after the global reset. A valid initialization sequence would be to clear

the PORT.CR1.PD bits in the ports that are to be active, write to all of the configuration registers to set them in the

desired modes, then clear the GL.CR1.RSTDP and PORT.CR1.RSTDP bits. This would cause the logic in the

ports to start up in a repeatable sequence. The device can also be initialized by clearing the GL.CR1.RSTDP,

PORT.CR1.RSTDP and PORT.CR1.PD them writing to all of the configuration registers to set them in the desired

modes, and clearing all of the latched status bits. The second initialization scheme could cause the device to

temporarily go into modes of operation that were not requested, but will quickly go into the requested modes of

operation.

Some of the IO pins are put in a known state at reset. The transmit LIU outputs TXPn and TXNn are quiet and will

not drive positive or negative pulses. The global IO pins (GPIO[7:0]) are set as inputs at global reset. The port

output pins (TLCLKn, TPOSn/TDATn, TNEGn, TOHCLKn, TOHSOFn, TSOFOn/TDENn, TCLKOn/TGCLKn,

ROHn, ROHCLKn, ROHSOFn, RSERn, RSOFOn/RDENn, RCLKOn/RGCLKn) are driven low at global or port

reset and should stay low until after the port power-down PORT.CR1.PD and port data path reset

PORT.CR1.RSTDP bits are cleared. The CLAD clock pins CLKA, CLKB and CLKC are the LIU reference clock

inputs at global reset. The processor port tri-state output pins (D[15:0],

RDY, INT) are forced into the high

impedance state when the

RST pin is active, but not when the GL.CR1.RST bit is active.

After reset, the device will be in the default configuration:: The latched status bits are enabled to be cleared on

write. The CLAD is disabled. The global 8KREF and one-second timers are disabled. The line interface is in B3ZS

mode and the LIU is disabled and the transmit line pins are also disabled. The frame mode is DS3 C-bit with

automatic downstream AIS on LOS or OOF is enabled and automatic RDI on LOF, LOS, SEF or AIS is enabled

DS3173N Datasheet(PDF) 62 Page - Dallas Semiconductor