DS3173N datasheet(32/232 Pages) DALLAS

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PIN NAME

TYPE

PIN DESCRIPTION

for the reference clock for the TSERn signal.

This signal can be inverted.

TSOFOn /

TDENn

Framer Start Of Frame / Data Enable

See Table 10-21.

TSOFOn: When the port framer is configured for the DS3 or E3 framed modes and

the TSOFOn pin function is selected, this signal is used to indicate the start of the

DS3/E3 frame on the TSERn pin. This signal pulses high three clocks before the first

overhead bit in a DS3 or E3 frame that will be input on TSERn. The signal is updated

on the positive clock edge of the referenced clock pin if the clock pin signal is not

inverted, otherwise it is updated on the falling edge of the clock. The signal is typically

referenced to the TCLKIn transmit clock input pins, but it can be referenced to the

TLCLKn, TCLKOn, RCLKOn and RLCLKn clock pins.

This signal can be inverted.

TDENn: When the port framer is configured for the DS3 or E3 framed modes and the

TDENn pin function is selected, this signal is used to mark the DS3/E3 frame bits on

the TSERn pin. The signal goes high three clocks before the start of DS3/E3 payload

bits and goes low three clocks before the end of the DS3/E3 payload bits. The signal

is updated on the positive clock edge of the referenced clock pin if the clock pin signal

is not inverted, otherwise it is updated on the falling edge of the clock. The signal is

typically referenced to the TCLKIn transmit clock input pins, but it can be referenced

to the TLCLKn, TCLKOn, RCLKOn and RLCLKn clock pins.

This signal can be inverted.

RSERn

Receive Serial Data

RSERn: When the port framer is configured for the DS3 or E3 framed modes, this pin

outputs the receive data signal from the LIU or receive line pins. The signal is updated

on the positive clock edge of the referenced clock pin if the clock pin signal is not

inverted, otherwise it is updated on the falling edge of the clock. The signal is typically

referenced to the RCLKOn receive clock output pin, but it can be referenced to the

RGCLKn and RLCLKn clock pins.

This signal can be inverted

DS3: 44.736 Mbps +20ppm

E3: 34.368 Mbps +20ppm

RCLKOn /

RGCLKn

Receive Clock Output / Gapped Clock

See Table 10-24.

RCLKOn: When the port framer is configured for the DS3 or E3 framed modes and

RCLKOn is selected, this clock output signal is active. It is the same as the internal

receive framer clock. This clock is typically used for the reference clock for the

RSERn, RSOFOn / RDENn signals but can also be used as the reference for the

RPOSn / RDATn, RNEGn / RLCVn, TSOFIn, TSERn, TSOFOn / TDENn, TPOSn /

TDATn and TNEGn signals.

This signal can be inverted.

DS3: 44.736 MHz +20 ppm

E3: 34.368 MHz +20 ppm

RGCLKn: When the port is configured for DS3/E3 framed mode and RGCLKn is

selected, this gated clock output signal is active. It is the same as the internal receive

framer clock gated by RDENn. This clock is typically used for the reference clock for

the RSERn.

This signal can be inverted

RSOFOn /

RDENn

Receive Framer Start Of Frame /Data Enable

See Table 10-23.

RSOFOn: When the port framer is configured for the DS3 or E3 framed modes and

the RSOFOn pin function is enabled, this signal is used to indicate the start of the

DS3/E3 frame. This signal indicates the first DS3/E3 overhead bit on the RSERn pin

when high. The signal is updated on the positive clock edge of the referenced clock

pin if the clock pin signal is not inverted, otherwise it is updated on the falling edge of

DS3173N Datasheet(PDF) 32 Page - Dallas Semiconductor

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