DS3173N datasheet(14/232 Pages) DALLAS

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FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or

two different codewords back-to-back to send DS3 Line Loopback commands

16-byte Trail Trace Buffer port for the G.832 trail access point identifier

Insertion of G.832 payload type, and timing marker bits from registers

DS3 M23 C bits configurable as payload or overhead, as overhead they can be controlled from registers or the

transmit overhead port

Most framing overhead fields can be sourced from transmit overhead port

Formatter bypass mode for clear channel or externally defined format applications

3.5 Transmit DS3/E3 LIU Features

Wide 50+20% transmit clock duty cycle

Line Build-Out (LBO) control

Tri-state line driver outputs support protection switching applications

Per-channel power-down control

Output driver monitor status indication

3.6 Jitter Attenuator Features

Fully integrated and requiring no external components

Can be placed in transmit or receive path

FIFO depth of 16 bits

Standard compliant transmission jitter and wander

3.7 Clock Rate Adapter Features

Generation of the internally needed DS3 (44.736 MHz) and E3 (34.368 MHz) clocks a from single input

reference clock

Input reference clock can be 51.84 MHz, 44.736MHz or 34.368 MHz

Internally derived clocks can be used as references for LIU and jitter attenuator

Derived clocks can be transmitted off-chip for external system use

Standards compliant jitter and wander requirements.

3.8 HDLC Overhead Controller Features

Each port has a dedicated HDLC controller for DS3/E3 framer link management

256-byte receive and transmit FIFOs

Handles all of the normal Layer 2 tasks including zero stuffing/de-stuffing, FCS generation/checking, abort

generation/checking, flag generation/detection, and byte alignment

Programmable high and low water marks for the transmit and receive FIFOs

Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode and optionally the G.751 Sn bit or the

G.832 NR or GC channels

RX data is forced to all ones during LOS, LOF and AIS detection to eliminate false packets

3.9 FEAC Controller Features

Each port has a dedicated FEAC controller for DS3/E3 link management

Designed to handle multiple FEAC codewords without Host intervention

Receive FEAC automatically validates incoming codewords and stores them in a 4-byte FIFO

Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different

codewords back-to-back to send DS3 Line Loopback commands

Terminates the FEAC channel in DS3 C-Bit Parity mode and optionally the Sn bit in E3 mode

3.10 Trail Trace Buffer Features

Each port has a dedicated Trail Trace Buffer for E3-G.832 link management

Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register

Insertion of the outgoing trail access point identifier from a 16-byte transmit register

DS3173N Datasheet(PDF) 14 Page - Dallas Semiconductor

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