DS3173N datasheet(10/232 Pages) DALLAS

10 / 232 page

DS3171/DS3172/DS3173/DS3174

10 of 230

LIST OF TABLES

Table 4-1. Standards Compliance ............................................................................................................................. 16

Table 7-1. HDB3/B3ZS/AMI LIU Mode Configuration Registers ............................................................................... 21

Table 7-2. HDB3/B3ZS/AMI Non-LIU Mode Configuration Registers ....................................................................... 23

Table 7-3. UNI Line Interface Mode Configuration Registers.................................................................................... 24

Table 8-1. DS3174 Short Pin Descriptions ................................................................................................................ 25

Table 8-2. Detailed Pin Descriptions ......................................................................................................................... 28

Table 9-1. Configuration of Port Register Settings .................................................................................................... 49

Table 10-1. LIU Enable Table.................................................................................................................................... 54

Table 10-2. All Possible Clock Sources Based on Mode and Loopback................................................................... 54

Table 10-3. Source Selection of TLCLK Clock Signal ............................................................................................... 55

Table 10-4. Source Selection of TCLKOn (internal TX clock) ................................................................................... 56

Table 10-5. Source Selection of RCLKO Clock Signal (internal RX clock) ............................................................... 56

Table 10-6. Transmit Line Interface Signal Pin Valid Timing Source Select............................................................. 57

Table 10-7. Transmit Framer Pin Signal Timing Source Select ................................................................................ 58

Table 10-8. Receive Line Interface Pin Signal Timing Source Select ....................................................................... 58

Table 10-9. Receive Framer Pin Signal Timing Source Select ................................................................................. 59

Table 10-10. Reset and Power-Down Sources ......................................................................................................... 62

Table 10-11. CLAD IO Pin Decode............................................................................................................................ 64

Table 10-12. Global 8 kHz Reference Source Table................................................................................................. 65

Table 10-13. Port 8 kHz Reference Source Table..................................................................................................... 65

Table 10-14. GPIO Global Signals ............................................................................................................................ 66

Table 10-15. GPIO Pin Global Mode Select Bits....................................................................................................... 66

Table 10-16. GPIO Port Alarm Monitor Select .......................................................................................................... 67

Table 10-17. Loopback Mode Selections .................................................................................................................. 69

Table 10-18. Line AIS Enable Modes ........................................................................................................................ 73

Table 10-19. Payload (downstream) AIS Enable Modes .......................................................................................... 74

Table 10-20. TSOFIn Input Pin Functions ................................................................................................................. 75

Table 10-21. TSOFOn/TDENn/Output Pin Functions................................................................................................ 75

Table 10-22. TCLKOn/TGCLKn Output Pin Functions.............................................................................................. 75

Table 10-23. RSOFOn/RDENn Output Pin Functions............................................................................................... 75

Table 10-24. RCLKOn/RGCLKn Output Pin Functions ............................................................................................. 76

Table 10-25. Framing Mode Select Bits FM[2:0] ....................................................................................................... 76

Table 10-26. Line Mode Select Bits LM[2:0].............................................................................................................. 77

Table 10-27. C-Bit DS3 Frame Overhead Bit Definitions .......................................................................................... 84

Table 10-28. M23 DS3 Frame Overhead Bit Definitions ........................................................................................... 86

Table 10-29. G.832 E3 Frame Overhead Bit Definitions ........................................................................................... 91

Table 10-30. Payload Label Match Status................................................................................................................. 95

Table 10-31. Pseudorandom Pattern Generation.................................................................................................... 108

Table 10-32. Repetitive Pattern Generation ............................................................................................................ 108

Table 10-33. Transformer Characteristics ............................................................................................................... 113

Table 10-34. Recommended Transformers............................................................................................................. 114

Table 11-1. Global and Test Register Address Map ............................................................................................... 117

Table 11-2. Per Port Register Address Map............................................................................................................ 118

Table 12-1. Global Register Bit Map........................................................................................................................ 119

Table 12-2. Port Register Bit Map ........................................................................................................................... 120

Table 12-3. BERT Register Bit Map ........................................................................................................................ 120

Table 12-4. Line Register Bit Map ........................................................................................................................... 121

Table 12-5. HDLC Register Bit Map ........................................................................................................................ 122

Table 12-6. FEAC Register Bit Map ........................................................................................................................ 122

Table 12-7. Trail Trace Register Bit Map................................................................................................................. 123

Table 12-8. T3 Register Bit Map.............................................................................................................................. 124

Table 12-9. E3 G.751 Register Bit Map................................................................................................................... 124

Table 12-10. E3 G.832 Register Bit Map................................................................................................................. 125

Table 12-11. Clear Channel Register Bit Map......................................................................................................... 126

Table 12-12. Global Register Map........................................................................................................................... 127

DS3173N Datasheet(PDF) 10 Page - Dallas Semiconductor

DS3173N Datasheet(HTML) 10 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL