DS3173N datasheet(36/232 Pages) DALLAS

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8.3 Pin Functional Timing

8.3.1 Line IO

8.3.1.1

B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing

There is no suggested time alignment between the TXPn, TXNn and TX LINE signals and the TLCLKn clock signal.

The TX DATA signal is not a readily available signal, it is meant to represent the data value of the other signals.

The TXPn and TXNn signals are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU is

enabled. The TPOSn, TNEGn and TLCLKn signals are only available when the line is in B3ZS/HDB3 or AMI mode

and the transmit line pins are enabled. The TPOSn, TNEGn and TLCLKn pins can be enabled at the same as the

LIU is enabled.

The TPOSn and TNEGn signals change a small delay after the positive edge of the reference clock if the clock pin

is not inverted; otherwise they change after the negative edge. The TLCLKn clock pin is the clock reference

typically used for the TPOSn and TNEGn signals, but they can be time referenced to the TCLKIn, TCLKOn,

RLCLKn or RCLKOn clock pins. The TPOSn and TNEGn pins can be inverted, but the polarity of TXPn and TXNn

cannot be inverted.

TXPn and TXNn are differential analog output pins. They are biased around ½ VDD and pulse above and below

the bias voltage by about 1 Volt. These signals are connected to the windings of a 1:2 step down transformer and

the other winding of the transformer creates the TX LINE signal. The TX LINE signal is a bipolar signal that pulses

about 1 Volt positive and 1 Volt negative above and below ground (0 volts). See Figure 1-1 for a diagram of the

external connections.

Figure 8-1 and Figure 8-2 show the relationship between the analog and the digital outputs.

Figure 8-1. TX Line IO B3ZS Functional Timing Diagram

TLCLK

TPOS

TNEG

(TX DATA)

B3ZS CODEWORD

(TX LINE)

TXP

TXN

0 V

BIAS V

DS3173N Datasheet(PDF) 36 Page - Dallas Semiconductor