DS3173N datasheet(98/232 Pages) DALLAS

98 / 232 page

DS3171/DS3172/DS3173/DS3174

98 of 231

packets, or there may be an end flag, inter-frame fill, and a start flag between packets. The flag check is performed

one bit at a time.

Inter-frame fill filtering removes the inter-frame fill between a start flag and an end flag. All inter-frame fill is

discarded. The inter-frame fill can be flags (01111110) or all '1's. When inter-frame fill is all ‘1’s, the number of '1's

between the end flag and the start flag may not be an integer number of bytes. When inter-frame fill is flags, the

number of bits between the end flag and the start flag will be an integer number of bytes (flags). Any time there is

less than 16 bits between two flags, the data will be discarded.

Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag, if

an abort sequence is detected, the packet is marked with an abort indication, and all subsequent data is discarded

until a packet start flag is detected. The abort sequence is seven consecutive ones.

Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag, if

an abort sequence is detected, the packet is marked with an abort indication, and all subsequent data is discarded

until a packet start flag is detected. The abort sequence is seven consecutive ones.

Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. After a start

flag is detected, destuffing is performed until an end flag is detected. Destuffing consists of discarding any '0' that

directly follows five contiguous '1's. After destuffing is completed, the serial bit stream is demultiplexed into an 8-bit

parallel data stream and passed on with packet start, packet end, and packet abort indications. If there is less than

eight bits in the last byte, an invalid packet status is set, and the packet is tagged with an abort indication. If a

packet ends with five contiguous '1's, the packet will be processed as a normal packet regardless of whether or not

the five contiguous '1's are followed by a '0'.

FCS processing checks the FCS, discards the FCS bytes, and marks FCS erred packets. The FCS is checked for

errors, and the last two bytes are removed from the end of the packet. If an FCS error is detected, the packet is

marked with an FCS error indication. The HDLC CONTROLLER performs FCS-16 checking. FCS processing is

programmable (on or off). If FCS processing is disabled, FCS checking is not performed, and all of the packet data

is passed on.

Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream

DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[0]

and the LSB in RFD[7] of the receive FIFO data RFD[7:0]. If bit reordering is enabled, the incoming 8-bit data

stream DT[1:8] is output to the Receive FIFO with the MSB in RFD[7] and the LSB in RFD[0] of the receive FIFO

data RFD[7:0]. DT[1] is the first bit received from the incoming data stream.

Once all of the packet processing has been completed, The 8-bit parallel data stream is passed on to the Receive

FIFO with packet start, packet end, and packet error indications.

10.7.6 Receive FIFO

The Receive FIFO block contains memory for 256 bytes of data with data status information and controller circuitry

for reading and writing the memory. The Receive FIFO Controller controls filling the memory, tracking the memory

fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow

conditions. The Receive FIFO accepts data and data status from the Receive Packet Processor and stores the

data along with data status information in memory. The data is read from the receive FIFO via the microprocessor

interface. The Receive FIFO also outputs FIFO fill status (empty/data available/full) via the microprocessor

interface. All operations are byte based. The Receive FIFO is considered empty when it does not contain any data.

The Receive FIFO is considered to have data available when there is a programmable number of bytes or more

stored in the memory. The Receive FIFO is considered full when it does not have any space available for storage.

The Receive FIFO accepts data from the Receive Packet Processor until full. If a packet start is received while full,

the data is discarded and a FIFO overflow condition is declared. If any other packet data is received while full, the

current packet being transferred is marked with an abort indication, and a FIFO overflow condition is declared.

Once a FIFO overflow condition is declared, the Receive FIFO will discard incoming data until a packet start is

received while the Receive FIFO has sixteen or more bytes available for storage. If the Receive FIFO is read while

the FIFO is empty, the read is ignored, and an invalid data indication given.

DS3173N Datasheet(PDF) 98 Page - Dallas Semiconductor

DS3173N Datasheet(HTML) 98 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL