DS3173N datasheet(35/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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PIN NAME

TYPE

PIN DESCRIPTION

JTMS

Ipu

JTAG Mode Select (with pull-up)

JTMS: This input signal is used to control the JTAG controller state machine and is

sampled on the rising edge of JTCLK.

JTDI

Ipu

JTAG Data Input (with pull-up)

JTDI: This input signal is used to input data into the register that is enabled by the

JTAG controller state machine and is sampled on the rising edge of JTCLK.

JTDO

JTAG Data Output

JTDO: This output signal is the output of an internal scan shift register enabled by the

JTAG controller state machine and is updated on the falling edge of JTCLK. The pin

is in the high impedance mode when a register is not selected or when the

JTRST

signal is high. The pin goes into and exits the high impedance mode after the falling

edge of JTCLK

JTRST

Ipu

JTAG Reset (active low with pullup)

JTRST: This input forces the JTAG controller logic into the reset state and forces the

JTDO pin into high impedance when low. This pin should be low while power is

applied and set high after the power is stable. The pin can be driven high or low for

normal operation, but must be high for JTAG operation.

CLAD

CLKA

Clock A

CLKA: This clock input is a DS3 signal(44.736MHz +/-20ppm) when the CLAD is

disabled or it is one of the CLAD reference clock signals when the CLAD is enabled.

CLKB

Clock B

CLKB: This pin is a E3(34.368 MHz +/-20 ppm) input signal when the CLAD is

disabled or it can be enabled to output a generated clock when the CLAD is enabled.

The pin is driven low when it is not selected to output a clock signal and the CLAD is

enabled. Refer to Table 10-11.

CLKC

Clock C

CLKC: This pin is a STS-1 (51.84 MHz +/-20ppm) input signal when the CLAD is

disabled or it can be enabled to output a generated clock when the CLAD is enabled.

The pin is driven low when it is not selected to output a clock signal and the CLAD is

enabled. Refer to Table 10-11.

POWER

VSS

PWR

Ground, 0 Volt potential

Common to digital core, digital IO and all analog circuits

VDD

PWR

Digital 3.3V

Common to digital core and digital IO

AVDDRn

PWR

Analog 3.3V for receive LIU on port n

Powers receive LIU on port n

AVDDTn

PWR

Analog 3.3V for transmit LIU on port n

Powers transmit LIU on port n

AVDDJn

PWR

Analog 3.3V for jitter attenuator on port n

Powers jitter attenuator on port n

AVDDC

PWR

Analog 3.3V for CLAD

Powers clock rate adapter common to all ports

DS3173N Datasheet(PDF) 35 Page - Dallas Semiconductor

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