DS3173N datasheet(34/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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PIN NAME

TYPE

PIN DESCRIPTION

INT: This interrupt signal is driven low when an event is detected on any of the

enabled interrupt sources in any of the register banks. When there are no active and

enabled interrupt sources, the pin can be programmed to either drive high or not drive

high. The reset default is to not drive high when there is no active and enabled

interrupt source. All interrupt sources are disabled when

RST=0 and they must be

programmed to be enabled.

MODE

Mode select

RD/WR or DS strobe mode

MODE: 1 = Data Strobe Mode, 0 = Read/Write Strobe Mode

WIDTH

Data bus width select 8 or 16-bit interface

WIDTH: 1 = 16-bits, 0 = 8 bits

Misc I/O

GPIO1

General-Purpose IO 1

GPIO1: This signal is configured to be a general-purpose IO pin, or an alarm output

signal for port 1.

GPIO2

General-Purpose IO 2

GPIO2: This signal is configured to be a general-purpose IO pin, or the 8KREFO

output signal, or an alarm output signal for port 1.

GPIO3

General-Purpose IO 3

GPIO3: This signal is configured to be a general-purpose IO pin, or an alarm output

signal for port 2.

GPIO4

General-Purpose IO 4

GPIO4: This signal is configured to be a general-purpose IO pin, or the 8KREFI input

signal, or an alarm output signal for port 2. When configured for 8KREFI mode the

signal frequency should be 8,000 Hz +/- 500 ppm and about 50% duty cycle.

GPIO5

General-Purpose IO 5

GPIO5: This signal is configured to be a general-purpose IO pin, or an alarm output

signal for port 3.

GPIO6

General-Purpose IO 6

GPIO6: This signal is configured to be a general-purpose IO pin, or the TMEI input

signal, or an alarm output signal for port 3. When configured for TMEI input, the signal

low time and high time must be greater than 500 ns.

GPIO7

General-Purpose IO 7

GPIO7: This signal is configured to be a general-purpose IO pin, or an alarm output

signal for port 4.

GPIO8

General-Purpose IO 8

GPIO8: This signal is configured to be a general-purpose IO pin, or the PMU input

signal, or an alarm output signal for port 4. When configured for PMU input, the signal

low time and high time must be greater than 500 ns.

TEST

Test enable (active low)

TEST: This signal enables the internal scan test mode when low. For normal operation

tie high. This is an asynchronous input.

HIZ

High impedance test enable (active low)

HIZ: This signal puts all digital output and bi-directional pins in the high impedance

state when it low and

JTRST is low. For normal operation tie high. This is an

asynchronous input.

RST

Reset (active low)

RST: This signal resets all the internal processor registers and logic when low. This

pin should be low while power is applied and set high after the power is stable. This is

an asynchronous input.

JTAG

JTCLK

JTAG Clock

JTCLK: This clock input is typically a low frequency (less than 10 MHz) 50% duty

cycle clock signal.

DS3173N Datasheet(PDF) 34 Page - Dallas Semiconductor

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