DS3173N datasheet(97/232 Pages) DALLAS

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register interface until full. If the Transmit FIFO is written to while the FIFO is full, the write is ignored, and a FIFO

overflow condition is declared. The Transmit Packet Processor reads the Transmit FIFO. If the Transmit Packet

Processor attempts to read the Transmit FIFO while it is empty, a FIFO underflow condition is declared.

10.7.4 Transmit HDLC Overhead Processor

The Transmit HDLC Overhead Processor accepts data from the Transmit FIFO, performs bit reordering, FCS

processing, stuffing, packet abort sequence insertion, and inter-frame padding.

A byte is read from the Transmit FIFO with a packet end status. When a byte is marked with a packet end

indication, the output data stream will be padded with FFh and marked with a FIFO empty indication if the Transmit

FIFO contains less than two bytes or transmit packet start is disabled. Transmit packet start is programmable (on

or off). When the Transmit Packet Processor reads the Transmit FIFO while it is empty, the output data stream is

marked with an abort indication. Once the Transmit FIFO is empty, the output data stream will be padded with

interframe fill until the Transmit FIFO contains two or more bytes of data and transmit packet start is enabled.

Bit reordering changes the bit order of each byte. If bit reordering is disabled, the outgoing 8-bit data stream

DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is input from the Transmit FIFO with the MSB in TFD[0]

and the LSB in TFD[7] of the transmit FIFO data TFD[7:0]. If bit reordering is enabled, the outgoing 8-bit data

stream DT[1:8] is input from the Transmit FIFO with the MSB in TFD[7] and the LSB in TFD[0] of the transmit FIFO

data TFD[7:0]. DT[1] is the first bit transmitted on the outgoing data stream.

FCS processing calculates an FCS and appends it to the packet. FCS calculation is a CRC-16 calculation over the

entire packet. The polynomial used for the CRC-16 is x

16 + x12 + x5 + 1. The CRC-16 is inverted after calculation,

and appended to the packet. For diagnostic purposes, an FCS error can be inserted. This is accomplished by

appending the calculated CRC-16 without inverting it. FCS error insertion is programmable (on or off). When FCS

processing is disabled, the packet is output without appending an FCS. FCS processing is programmable (on or

off).

Stuffing inserts control data into the packet to prevent packet data from mimicking flags. Stuffing is halted during

FIFO empty periods. The 8-bit parallel data stream is multiplexed into a serial data stream, and bit stuffing is

performed. Bit stuffing consists of inserting a '0' directly following any five contiguous '1's. Stuffing is performed

from a packet start until a packet end.

Inter-frame padding inserts inter-frame fill between the packet start and end flags when the FIFO is empty. The

inter-frame fill can be flags or '1's. If the inter-frame fill is flags, flags (minimum two) are inserted until a packet start

is received. If the inter-frame fill is all '1's, an end flag is inserted, ‘1’s are inserted until a packet start is received,

and a start flag is inserted after the ‘1’s. The number of '1's between the end flag and start flag may not be an

integer number of bytes, however, the inter-frame fill will be at least 15 consecutive '1's. If the FIFO is not empty

between a packet end and a packet start, then two flags are inserted between the packet end and packet start. The

inter-frame padding type is programmable (flags or ‘1’s).

Packet abort insertion inserts a packet abort sequences as necessary. If a packet abort indication is detected, a

packet abort sequence is inserted and inter-frame padding is done until a packet start is detected. The abort

sequence is FFh.

Once all packet processing has been completed, the datastream is inserted into the DS3/E3 datastream at the

proper locations. If transmit data inversion is enabled, the outgoing data is inverted after packet processing is

performed. Transmit data inversion is programmable (on or off).

10.7.5 Receive HDLC Overhead Processor

The Receive HDLC Overhead Packet Processor accepts data from the DS3/E3 Framer and performs packet

delineation, inter-frame fill filtering, packet abort detection, destuffing, FCS processing, and bit reordering. If receive

data inversion is enabled, the incoming data is inverted before packet processing is performed. Receive data

inversion is programmable (on or off).

Packet delineation determines the packet boundary by identifying a packet start flag. Each time slot is checked for

a flag sequence (7Eh). Once a flag is found, if it is identified as a start or end flag, and the packet boundary is set.

There may be a single flag (both end and start) between packets, there may be an end flag and a start flag with a

shared zero (011111101111110) between packets, there may be an end flag and a start flag (two flags) between

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