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FXLS93421 Datasheet(PDF) 186 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 186 Page - NXP Semiconductors |
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186 / 254 page ![]() NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Time (µs) 0 500 400 200 300 tLAT_INTERP + tLAT_DSI tPDCM_RSPSTx 100 600 1000 800 900 700 aaa-030676 Figure 91. Simultaneous sampling mode 13.5.3 Synchronous sampling mode with minimum latency The device can be programmed to respond in synchronous sampling mode with minimum latency by programming the SS_EN bit to "Synchronous Sampling Mode". In synchronous sampling mode, the most recent interpolated sensor data sample is latched at the time programmed in the PDCM_RSPSTx registers, relative to tTRIG (rising edge of Sync pulse). The data is transmitted starting at the time programmed in the PDCM_RSPSTx registers, relative to tTRIG. Time (µs) 0 500 400 200 300 tPDCM_RSPSTx 100 600 1000 800 900 700 aaa-030677 tLAT_INTERP + tLAT_PSI5 Figure 92. Synchronous sampling mode with minimum latency 13.6 PSI5 default mode (un-programmed PSI5 device) Un-programmed FXLS93xxx PSI5 devices include a default PSI5 transmission mode. The devices will respond to PSI5 sync pulses and transmit data in PSI5-P16C-500/2L mode with the minimum user gain and the default 400 Hz, 4-Pole low-pass filter. FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 186 / 254 |
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