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FXLS93421 Datasheet(PDF) 189 Page - NXP Semiconductors

Part # FXLS93421
Description  Dual channel inertial sensor
PDF  254 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS93421 Datasheet(HTML) 189 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
SID1_EN SID0_EN Response start time
Response format
Start
CH1_SNSDATA0
CH0_SNSDATA0
P
PDCM_RSTST0
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 P
0
1
PDCM_RSTST1
No Transmission
PDCM_RSTST0
No Transmission
Start
CH1_SNSDATA1
CH0_SNSDATA1
P
1
0
PDCM_RSTST1
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 P
Start
CH1_SNSDATA0
CH0_SNSDATA0
P
PDCM_RSTST0
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 P
Start
CH1_SNSDATA1
CH0_SNSDATA1
P
1
1
PDCM_RSTST1
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 P
Table 275. Dual transmission mode 16-bit transmission data with parity...continued
SID1_EN SID0_EN Response start
time
Response format
PDCM_RSTST0
No Transmission
0
0
PDCM_RSTST1
No Transmission
Start
CH1_SNSDATA0
CH0_SNSDATA0
CRC
PDCM_RSTST0
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 C2 C1 C0
0
1
PDCM_RSTST1
No Transmission
PDCM_RSTST0
No Transmission
Start
CH1_SNSDATA1
CH0_SNSDATA1
CRC
1
0
PDCM_RSTST1
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 C2 C1 C0
Start
CH1_SNSDATA0
CH0_SNSDATA0
CRC
PDCM_RSTST0
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 C2 C1 C0
Start
CH1_SNSDATA1
CH0_SNSDATA1
CRC
1
1
PDCM_RSTST1
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 C2 C1 C0
Table 276. Dual transmission mode 16-bit transmission data with CRC
13.8 Daisy chain mode
The device can be programmed to operate in daisy chain mode by setting the
DAISY_CHAIN bit in the PSI5_CFG register. Daisy chain mode can be programmed to
operate in either "Simultaneous Sampling Mode", or "Synchronous Sampling Mode" by
setting the SS_EN bit to the desired operating mode. In simultaneous sampling mode,
the most recent interpolated sensor data sample is latched at tTRIG (rising edge of Sync
Pulse). In synchronous sampling mode, the most recent interpolated sensor data sample
is latched at the transmission time associated with the programmed sensor address,
relative to tTRIG (rising edge of Sync pulse).
When programmed to operate in daisy chain mode, the device follows the procedure:
FXLS9xxxx
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
189 / 254



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