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FXLS93421 Datasheet(PDF) 191 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 191 Page - NXP Semiconductors |
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191 / 254 page ![]() NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Response code Definition Value SAdr Programmed Sensor Address, prepended with logic zeros. Varies Table 279. Daisy chain programming response code definitions...continued Sensor address (SAdr) A2 A1 A0 Description Time slot source ID 0 Time slot source ID 2 0 0 0 Un-programmed sensor N/A N/A 0 0 1 Sensor Address 1 tTIMESLOT_DC0 tTIMESLOT_DC1_L 0 1 0 Sensor Address 2 tTIMESLOT_DC1_L tTIMESLOT_DC2_L 0 1 1 Sensor Address 3 tTIMESLOT_DC2_L tTIMESLOT_DC0 1 0 0 Sensor Address 4 tTIMESLOT_DC1_H tTIMESLOT_DC2_H 1 0 1 Sensor Address 5 tTIMESLOT_DC2_H tTIMESLOT_DC3_H 1 1 0 Sensor Address 6 tTIMESLOT_DC3_H tTIMESLOT_DC0 1 1 1 N/A N/A N/A Table 280. Valid daisy chain addresses Note: Writes to Sensor Address 7 are ignored. Note: If a successful programming mode entry command is received prior to a set address, daisy chain mode is disabled. 13.9 Error handling 13.9.1 Daisy chain error handling Table 281 shows the effect of internal failure modes on the daisy chain initialization procedure. Error condition Effect on daisy chain Supply Error Daisy chain commands ignored. The device will not participate in daisy chain. Communication Error No effect. The device will participate in Daisy Chain as programmed. Test Mode Enabled Daisy chain commands ignored. The device will not participate in daisy chain. Offset Error No effect. The device will participate in daisy chain as programmed. Temperature Error No effect. The device will participate in daisy chain as programmed. Memory Error No effect. The device will participate in daisy chain as programmed. Self-test Error No effect. The device will participate in daisy chain as programmed. Device Not Locked No effect. The device will participate in daisy chain as programmed. Table 281. Daisy chain error handling 13.9.2 Initialization phase 2 error handling Table 282 shows the effect of internal failure modes on the initialization phase 2 transmissions. Some errors occurring in initialization phase 2 will prevent entry into FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 191 / 254 |
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