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FXLS93421 Datasheet(PDF) 188 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 188 Page - NXP Semiconductors |
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188 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Parameter Value Default register bit values Sensor data range 232.6 g $40, $48: CHx_CFG_U1[1:0] = 2'b00 Sensor data sensitivity 132.06 LSB/g $41, $49: CHx_CFG_U2[7:0] = 0x00 Sensor data low-pass filter 400 Hz, 4-Pole LPF $40, $48: CHx_CFG_U1[7:4] = 4'b0000 Sensor data offset cancellation 0.04 Hz, 1-Pole HPF with Rate Limiting Enabled $43, $4B: CHx_CFG_U4[5:4] = 2'b00 Table 272. Default PSI5-P16C transmission mode, Medium g sensor data configuration 13.7 Dual transmission mode The device can be programmed to transmit both channel 0 and channel 1 data in one data packet if the DUALTRANS bit is set in the PSI5_CFG register. In dual transmission mode, the source identification settings specified in Section 11.2.17.4 determine the data transmitted as shown in Table 273 through Table 276. SID1_EN SID0_EN Response start time Response format PDCM_RSTST0 No Transmission 0 0 PDCM_RSTST1 No Transmission Start Bits CH1_SNSDATA0 CH0_SNSDATA0 Parity PDCM_RSTST0 S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 P 0 1 PDCM_RSTST1 No Transmission PDCM_RSTST0 No Transmission Start Bits CH1_SNSDATA1 CH0_SNSDATA1 Parity 1 0 PDCM_RSTST1 S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 P Start Bits CH1_SNSDATA0 CH0_SNSDATA0 Parity PDCM_RSTST0 S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 P Start Bits CH1_SNSDATA1 CH0_SNSDATA1 Parity 1 1 PDCM_RSTST1 S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 P Table 273. Dual transmission mode 10-bit transmission data with parity SID1_EN SID0_EN Response start time Response format PDCM_RSTST0 No Transmission 0 0 PDCM_RSTST1 No Transmission Start Bits CH1_SNSDATA0 CH0_SNSDATA0 CRC PDCM_RSTST0 S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 C2 C1 C0 0 1 PDCM_RSTST1 No Transmission PDCM_RSTST0 No Transmission Start Bits CH1_SNSDATA1 CH0_SNSDATA1 CRC 1 0 PDCM_RSTST1 S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 C2 C1 C0 Start Bits CH1_SNSDATA0 CH0_SNSDATA0 CRC PDCM_RSTST0 S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 C2 C1 C0 Start Bits CH1_SNSDATA1 CH0_SNSDATA1 CRC 1 1 PDCM_RSTST1 S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 C2 C1 C0 Table 274. Dual transmission mode 10-bit transmission data with CRC SID1_EN SID0_EN Response start time Response format PDCM_RSTST0 No Transmission 0 0 PDCM_RSTST1 No Transmission Table 275. Dual transmission mode 16-bit transmission data with parity FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 188 / 254 |
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