FXLS93421 datasheet(185/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Note: If self-test has completed all retries and has failed before F10, D33 is to be

transmitted, F10, D33 - D48 will include self-test data from the last failed attempt.

Note: In PSI5 asynchronous mode, self-test will not be complete prior to the

transmission of the F10. Setting the INIT2_EXT bit will result in invalid self-test data in

D33 and D34 (0x0 values).

Note: Constant values are transmitted for all fields marked as "RESERVED"

13.4.3 Internal self-test

Once Initialization Phase 1 completes, the device begins its internal self-test as

described in Section 11.6.2.5. If self-test fails, the device repeats self-test up to ST_RPT

times.

13.4.4 Initialization phase 3

During PSI5 initialization phase 3, the device completes its internal self-checks, and

transmits a combination of "Sensor Busy" or "Sensor Ready" messages as defined in

Table 264. The number of "Sensor Busy" messages transmitted in initialization phase

3 varies depending on the mode of operation, and the number of self-test repetitions.

Self-test is repeated on failure up to ST_RPT times to provide immunity to misuse

inputs during initialization. Self-test terminates successfully after one successful self-test

sequence.

Once internal self-test is completed, the device transmits 2 "Sensor Ready" commands.

Note: Self-test repeats are handled independently for each channel. However, both

channels will exit initialization phase 3 simultaneously. If only one channel is repeating

self-tests, both channels transmit "Sensor Busy" commands until either self-test has

passed on both channels or the total number of repeats have completed.

The ENDINIT bit is automatically set when the device exits Initialization Phase 3.

13.5 Normal mode

13.5.1 Asynchronous mode

The device can be programmed to respond in asynchronous mode as specified in

Section 11.2.18.1.

In asynchronous mode, the device transmits data at a fixed rate (tASYNC) and will not

respond to normal sync pulses. However, during initialization phase 1, the device will

monitor sync pulses to decode the programming mode entry command and allow entry

into programming mode.

13.5.2 Simultaneous sampling mode

The device can be programmed to respond in simultaneous sampling mode by

programming the SS_EN bit to "Simultaneous Sampling Mode".

In simultaneous sampling mode, the most recent interpolated sensor data sample

is latched at tTRIG (rising edge of Sync Pulse) and transmitted starting at the time

programmed in the PDCM_RSPSTx registers, relative to tTRIG.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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