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FXLS93421 Datasheet(PDF) 183 Page - NXP Semiconductors

Part # FXLS93421
Description  Dual channel inertial sensor
PDF  254 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS93421 Datasheet(HTML) 183 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
PSI5
field ID #
PSI5
nibble ID #
Page
address
PSI5 nibble address
Register address
PSI5 description
Value
D19
0010
SN4[7:4] or USERDATA_6[7:4]
Data determined by PSI5_INIT2_D19 in
TIMING_CFG2 register
User
D20
0011
SN4[3:0] or USERDATA_E[7:4]
Data determined by PSI5_INIT2_D19 in
TIMING_CFG2 register
User
D21
0100
SN3[7:4]
Device Serial Number
Factory
D22
0101
SN3[3:0]
Device Serial Number
Factory
D23
0110
SN2[7:4]
Device Serial Number
Factory
D24
0111
SN2[3:0]
Device Serial Number
Factory
D25
1000
SN1[7:4]
Device Serial Number
Factory
D26
1001
SN1[3:0]
Device Serial Number
Factory
D27
1010
SN0[7:4]
Device Serial Number
Factory
D28
1011
SN0[3:0]
Device Serial Number
Factory
D29
1100
PN1[3:0]
Device Part Number
Factory
D30
1101
PN0[7:4]
Device Part Number
Factory
D31
1110
PN0[3:0]
Device Part Number
Factory
F9
D32
1111
USERDATA_6[7:4]
User Specific Data
User
D33
0000
CH0_STAVG_P[7:4]
Channel 0 Positive Self-test, High Nibble
Varies
D34
0001
CH0_STAVG_P[3:0]
Channel 0 Positive Self-test, Low Nibble
Varies
D35
0010
CH0_STOFFSET_P[7:4]
Channel 0 Post Positive Self-test Offset, High
Nibble
Varies
D36
0011
CH0_STOFFSET_P[3:0]
Channel 0 Post Positive Self-test Offset, Low
Nibble
Varies
D37
0100
CH0_STAVG_N[7:4]
Channel 0 Negative Self-test, High Nibble
Varies
D38
0101
CH0_STAVG_N[3:0]
Channel 0 Negative Self-test, Low Nibble
Varies
D39
0110
CH0_STOFFSET_N[7:4]
Channel 0 Post Negative Self-test Offset, High
Nibble
Varies
D40
0111
CH0_STOFFSET_N[3:0]
Channel 0 Post Negative Self-test Offset, Low
Nibble
Varies
D41
1000
CH1_STAVG_P[7:4]
Channel 1 Positive Self-test, High Nibble
Varies
D42
1001
CH1_STAVG_P[3:0]
Channel 1 Positive Self-test, Low Nibble
Varies
D43
1010
CH1_STOFFSET_P[7:4]
Channel 1 Post Positive Self-test Offset, High
Nibble
Varies
D44
1011
CH1_STOFFSET_P[3:0]
Channel 1 Post Positive Self-test Offset, Low
Nibble
Varies
D45
1100
CH1_STAVG_N[7:4]
Channel 1 Negative Self-test, High Nibble
Varies
D46
1101
CH1_STAVG_N[3:0]
Channel 1 Negative Self-test, Low Nibble
Varies
D47
1110
CH1_STOFFSET_N[7:4]
Channel 1 Post Negative Self-test Offset, High
Nibble
Varies
F10
D48
2
1111
CH1_STOFFSET_N[3:0]
Channel 1 Post Negative Self-test Offset, Low
Nibble
Varies
Table 267. Channel 0 PSI5 initialization phase 2 data...continued
PSI5
field ID #
PSI5
nibble ID #
Page
address
PSI5 nibble address
Register address
Description
Value
F1
D1
0000
USERDATA_0[7:4]
User Specific Data
User
F2
D2, D3
0001, 0010
NA
Number of Data Blocks: 32: INIT2_EXT = 0, 48:
INIT2_EXT = 1
0010 0000
or
0011 0000
F3
D4, D5
0011, 0100
USERDATA_9[3:0], USERDATA_9[7:4]
User Specific Data
User
F4
D6, D7
0101, 0110
USERDATA_A[3:0], USERDATA_A[7:4]
User Specific Data
User
D8
0111
USERDATA_B[3:0]
User Specific Data
User
F5
D9
1000
USERDATA_B[7:4]
User Specific Data
User
D10
1001
USERDATA_C[3:0]
User Specific Data
User
F6
D11
0
1010
USERDATA_C[7:4]
User Specific Data
User
Table 268. Channel 1 PSI5 Initialization Phase 2 Data
FXLS9xxxx
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
183 / 254



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