FXLS93421 datasheet(210/254 Pages) NXP

210 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

MSB

LSB

Error Response to Sensor Data Request Without Sensor Data

Command

Basic

Status

Unused Data = 0x0000

Detail

Status

Unused Data = 0x00

3-bit CRC

SF[1:0]

CRC[2:0]

Table 328. SPI response format with 3-bit CRC...continued

14.4.3.3 Command error checking with 3-bit CRC

The device calculates a 3-bit CRC on the entire 32-bits of each command. Message data

is entered into the CRC calculator MSB first, consistent with the transmission order of the

message. If the calculated CRC does not match the transmitted CRC, the command is

ignored and the device responds with the SPI Error response.

The CRC decoding procedure is:

1. A seed value determined by the SPICRCSEED[2:0] value in the SPI_CFG register is

preset into the least significant bits of the shift register.

2. Using a serial CRC calculation method, the receiver rotates the received message

and CRC into the least significant bits of the shift register in the order received (MSB

first).

3. When the calculation on the last bit of the CRC is rotated into the shift register, the

shift register contains the CRC check result.

4. If the shift register contains all zeros, the CRC is correct.

5. If the shift register contains a value other than zero, the CRC is incorrect.

The CRC polynomial and seed are shown in Table 329.

Default polynomial

Non-direct seed

x3 + x + 1

SPICRCSEED[2:0]

Table 329. SPI command message CRC, 3 bit

Some example CRC calculations are shown in Table 263.

14.4.3.4 Response error checking with 3-bit CRC

The device calculates a CRC on the entire 32-bits of each response. Message data is

entered into the CRC calculator MSB first, consistent with the transmission order of the

message.

The CRC encoding procedure is:

1. A seed value determined by the SPICRCSEED[2:0] value is preset into the least

significant bits of the shift register.

2. Using a serial CRC calculation method, the transmitter rotates the transmitted

message into the least significant bits of the shift register, MSB first.

3. Following the transmitted message, the transmitter feeds three zeros into the shift

4. When the last zero is fed into the input adder, the shift register contains the CRC.

5. The CRC is transmitted.

The CRC polynomial and seed are shown in Table 330.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

210 / 254

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