FXLS93421 datasheet(208/254 Pages) NXP

208 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

1. A seed value determined by the SPICRCSEED[3:0] value in the SPI_CFG register is

preset into the least significant bits of the shift register.

2. Using a serial CRC calculation method, the receiver rotates the received message

and CRC into the least significant bits of the shift register in the order received (MSB

first).

3. When the calculation on the last bit of the CRC is rotated into the shift register, the

shift register contains the CRC check result.

4. If the shift register contains all zeros, the CRC is correct.

5. If the shift register contains a value other than zero, the CRC is incorrect.

The CRC polynomial and seed are shown in Table 324.

Default polynomial

Non-direct seed

x4 + 1

SPICRCSEED[3:0]

Table 324. SPI command message CRC, 4 bit

14.4.2.4 Response error checking with 4-bit CRC

The device calculates a CRC on the entire 32-bits of each response. Message data is

entered into the CRC calculator MSB first, consistent with the transmission order of the

message.

The CRC Encoding procedure is:

1. A seed value determined by the SPICRCSEED[3:0] value is preset into the least

significant bits of the shift register.

2. Using a serial CRC calculation method, the transmitter rotates the transmitted

message into the least significant bits of the shift register, MSB first.

3. Following the transmitted message, the transmitter feeds four zeros into the shift

4. When the last zero is fed into the input adder, the shift register contains the CRC.

5. The CRC is transmitted.

The CRC polynomial and seed are shown in Table 325.

Default polynomial

Non-direct seed

x4 + 1

SPICRCSEED[3:0]

Table 325. SPI response message CRC, 4-bit

14.4.2.5 Message counter (KAC) with 4-bit CRC

If the 4-bit CRC is enabled, a 4-bit message counter field (KAC) is added to the Sensor

Data Request Response. The message counter field is a 4-bit rolling message counter

that is independently incremented for each SOURCEID. The initial value of the counter is

'0001'.

14.4.2.6 Example 4-bit CRC calculations

Some example CRC calculations for 32-bit SPI commands are shown in Table 326.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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