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CEC1712 Datasheet(PDF) 172 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 172 Page - Microchip Technology |
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172 / 338 page ![]() CEC1712 DS00003416C-page 172 2020-2021 Microchip Technology Inc. 14.10.3 CAPTURE CONTROL 1 REGISTER 7:5 FCLK_SEL0 This 3-bit field sets the clock source for the input filter for Capture Register 0. See Table 14-2, "Timer Clock Frequencies" for a list of available frequencies. R/W 0h RESET _SYS 4:3 Reserved RES - - 2 FILTER_BYP0 This bit enables bypassing the input noise filter for Capture Regis- ter 0, so that the input signal goes directly into the timer. 1=Input filter bypassed 0=Input filter enabled R/W 0h RESET _SYS 1:0 CAPTURE_EDGE0 This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 0. 3=Capture event disabled 2=Both rising and falling edges 1=Rising edges 0=Falling edges R/W 0h RESET _SYS Offset 08h Bits Description Type Default Reset Event 31:16 Reserved RES - - 15:13 FCLK_SEL5 This 3-bit field sets the clock source for the input filter for Capture Register 5. See Table 14-2, "Timer Clock Frequencies" for a list of available frequencies. R/W 0b RESET _SYS 12:11 Reserved RES - - 10 FILTER_BYP5 This bit enables bypassing the input noise filter for Capture Regis- ter 5, so that the input signal goes directly into the timer. 1=Input filter bypassed 0=Input filter enabled R/W 0h RESET _SYS Offset 04h Bits Description Type Default Reset Event |
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