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CEC1712 Datasheet(PDF) 170 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 170 Page - Microchip Technology |
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170 / 338 page  CEC1712 DS00003416C-page 170 2020-2021 Microchip Technology Inc. 14.10.2 CAPTURE CONTROL 0 REGISTER 2 FREE_RESET Free Running Timer Reset. This bit stops the timer and resets the internal counter to 0000_0000h. This bit does not affect the FREE_ENABLE bit. This bit is self clearing after the timer is reset. 1=Timer reset 0=Normal timer operation R/W 0h RESET _SYS 1 FREE_ENABLE Free-Running Timer Enable. This bit is used to start and stop the free running timer. This bit does not reset the timer count. The timer starts counting at 0000_0000h on reset and wraps around back to 0000_0000h after it reaches FFFF_FFFFh. The FREE_ENABLE bit is cleared after the RESET cycle is done. Firmware must poll the FREE_RESET bit to determine when it is safe to re-enable the timer. 1=Timer is enabled. The Free Running Timer Register is read-only. 0=Timer is disabled. The Free Running Timer Register is writable. R/W 0h RESET _SYS 0 ACTIVATE 1=The timer block is in a running state 0=The timer block is powered down and all clocks are gated R/W 0h RESET _SYS Offset 04h Bits Description Type Default Reset Event 31:29 FCLK_SEL3 This 3-bit field sets the clock source for the input filter for Capture Register 3. See Table 14-2, "Timer Clock Frequencies" for a list of available frequencies. R/W 0h RESET _SYS 28:27 Reserved RES - - 26 FILTER_BYP3 This bit enables bypassing the input noise filter for Capture Regis- ter 3, so that the input signal goes directly into the timer. 1=Input filter bypassed 0=Input filter enabled R/W 0h RESET _SYS Offset 00h Bits Description Type Default Reset Event |
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