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CEC1712 Datasheet(PDF) 169 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 169 Page - Microchip Technology |
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169 / 338 page  2020-2021 Microchip Technology Inc. DS00003416C-page 169 CEC1712 24 COMPARE_CLEAR1 When read, returns the current value off the Compare Timer Out- put 1 state. If written with a ‘1b’, the output state is cleared to ‘0’. Writes have no effect if COMPARE_SET0 in this register is written with a ‘1b’ at the same time. Writes of ‘0b’ have no effect. R/WC 0 RESET _SYS 23:18 Reserved RES - - 17 COMPARE_SET0 When read, returns the current value off the Compare Timer Out- put 0 state. • If written with a ‘1b’, the output state is set to ‘1’. • Writes of ‘0b’ have no effect R/WS 0 RESET _SYS 16 COMPARE_SET1 When read, returns the current value off the Compare Timer Out- put 1 state. If written with a ‘1b’, the output state is set to ‘1’. Writes of ‘0b’ have no effect R/WS 0 RESET _SYS 15:10 Reserved RES - - 9 COMPARE_ENABLE1 Compare Enable for Compare 1 Register. When enabled, a match between the Compare 1 Register and the Free Running Timer Register will cause the TOUT1 output to toggle and will send a COMPARE event to the Interrupt Aggregator. 1=Enabled 0=Disabled R/W 0b RESET _SYS 8 COMPARE_ENABLE0 Compare Enable for Compare 0 Register. When enabled, a match between the Compare 0 Register and the Free Running Timer Register will cause the TOUT0 output to toggle and will send a COMPARE event to the Interrupt Aggregator. 1=Enabled 0=Disabled R/W 0b RESET _SYS 7 Reserved RES - - 6:4 TCLK This 3-bit field sets the clock source for the Free-Running Counter. See Table 14-2, "Timer Clock Frequencies" for a list of available frequencies. R/W 0b RESET _SYS 3 Reserved RES - - Offset 00h Bits Description Type Default Reset Event |
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