CEC1712 datasheet(167/338 Pages) MICROCHIP

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DS00003416C-page 167

CEC1712

14.8.1

TIMER CLOCK

Any of the frequencies listed in Table 14-2 may be used as the time base for the Free Running Counter.

For the Timer Clock, the Timer Clock Select value is defined by the TCLK field in the Capture and Compare Timer

Control Register

14.8.2

FILTER CLOCK AND NOISE FILTER

The noise filter uses the Filter Clock (FCLK) to filter the signal on the Input Capture pins. An Input Capture pin must

remain in the same state for three FCLK ticks before the internal state changes. The FILTER_BYPASS bit for the Input

Capture pin may be used to bypass the input filter. Each Capture Register can individually bypass the filter.

When the input filter is bypassed, the minimum period of FCLK must be at least 2X the duration of an input signal pulse

in order for an edge event to be captured reliably. When the input filter is enabled, the minimum period of FCLK must

be at least 4X the duration of an input signal pulse in order for an edge event to be captured reliably.

14.9

Operation

14.9.1

INPUT CAPTURE

The Input Capture block consists of a free-running 32-bit timer and 2 capture registers. Each of the capture registers is

associated with an input pin as well as an interrupt source bit in the Interrupt Aggregator: The Capture registers store

the current value of the Free Running timer whenever the associated input signal changes, according to the pro-

grammed edge detection. An interrupt is also generated to the EC. The Capture registers are read-only. The registers

are updated every time an edge is detected. If software does not read the register before the next edge, the value is lost.

14.9.2

COMPARE TIMER

There are two 32-bit Compare registers. Each of these registers can independently generate an interrupt to the EC when

the 32-bit Free Running Timer matches the contents of the Compare register. The compare operation for each is

enabled or disabled by a bit in the Capture and Compare Timer Control Register.

14.9.2.1

Interrupt Generation

Whenever a Compare Timer is enabled and the Compare register matches the Free Running Timer, a COMPARE event

is sent to the Interrupt Aggregator. The event will trigger an EC interrupt if enabled by the appropriate Interrupt Enable

14.9.2.2

Compare Output Generation

Each Compare Timer is associated with a toggle flip-flop. When the 32-bit Free Running Timer matches the contents of

the Compare register the output off the flip-flop is complemented. Each of the toggle flip-flops can be independently set

or cleared by using the COMPARE_SET or COMPARE_CLEAR fields, respectively, in the Capture and Compare Timer

Control Register.

A Compare Timer should be disabled before setting or clearing the output, when updating the Compare register, or when

updating the Free Running Timer, so spurious events are not generated by the matcher.

TABLE 14-2:

TIMER CLOCK FREQUENCIES

Timer Clock Select

Frequency Divide Select

Frequency Selected

0000b

Divide by 1

48MHz

0001b

Divide by 2

24MHz

0010b

Divide by 4

12MHz

0011b

Divide by 8

6MHz

0100b

Divide by 16

3MHz

0101b

Divide by 32

1.5MHz

0110b

Divide by 64

750KHz

0111b

Divide by 128

375KHz

1xxxb

Reserved

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