CEC1712 datasheet(164/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 164

 2020-2021 Microchip Technology Inc.

14.0 INPUT CAPTURE AND COMPARE TIMER

14.1

Introduction

The Input Capture and Compare Timers block contains a 32-bit timer running at the main system clock frequency. The

timer is free-running and is associated with six 32-bit capture registers and two compare registers. Each capture register

can record the value of the free-running timer based on a programmable edge of its associated input pin. An interrupt

can be generated for each capture register each time it acquires a new timer value. The timer can also generate an

interrupt when it automatically resets and can additionally generate two more interrupts when the timer matches the

value in either of two 32-bit compare registers.

14.2

Interface

This block is designed to be accessed externally via the pin interface and internally via a registered host interface.

14.3

Signal Description

14.4

Host Interface

The registers defined for 16-bit Timers are accessible by the various hosts as indicated in Section 3.2, "Block Overview

and Base Addresses".

FIGURE 14-1:

I/O DIAGRAM OF BLOCK

TABLE 14-1:

SIGNAL DESCRIPTION

Name

Direction

Description

ICTx

INPUT

External capture trigger signal for Capture Register.

CTOUT0

OUTPUT

External compare match signal for Compare Register 0

CTOUT1

OUTPUT

External compare match signal for Compare Register 1

Note:

Any ICTx can be connected to any Capture register using the ICT MUX Select Register.

Signal Description

Input Capture and Compare

Timer

Interrupts

Power, Clocks and Reset

Host Interface

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