CEC1712 datasheet(165/338 Pages) MICROCHIP

165 / 338 page

 2020-2021 Microchip Technology Inc.

DS00003416C-page 165

CEC1712

14.5

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

14.5.1

POWER DOMAINS

14.5.2

CLOCK INPUTS

14.5.3

RESETS

14.6

Interrupts

This section defines the Interrupt Sources generated from this block.

Name

Description

VTR_CORE

The logic and registers implemented in this block are powered by this

power well.

Name

Description

48MHz

This is the clock source for this block.

Name

Description

RESET_SYS

This signal resets all the registers and logic in this block to their default

state.

Source

Description

CAPTURE TIMER

This interrupt event fires when the 32-bit free running counter overflows

from FFFF_FFFFh to 0000_0000h.

CAPTURE 0

This interrupt event fires when Capture Register 0 acquires a new value.

CAPTURE 1

This interrupt event fires when Capture Register 1 acquires a new value.

CAPTURE 2

This interrupt event fires when Capture Register 2 acquires a new value.

CAPTURE 3

This interrupt event fires when Capture Register 3 acquires a new value.

CAPTURE 4

This interrupt event fires when Capture Register 4 acquires a new value.

CAPTURE 5

This interrupt event fires when Capture Register 5 acquires a new value.

COMPARE 0

This interrupt event fires when the contents of Compare 0 Register

match the contents of the Free Running Counter.

COMPARE 1

This interrupt event fires when the contents of Compare 1 Register

match the contents of the Free Running Counter.

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