CEC1712 datasheet(166/338 Pages) MICROCHIP

166 / 338 page

CEC1712

DS00003416C-page 166

 2020-2021 Microchip Technology Inc.

14.7

Low Power Modes

The Capture and Compare Timer may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) cir-

cuitry. This block is only be permitted to enter low power modes when the block is not active. The block is inactive if the

ACTIVATE bit is de-asserted, and will also become inactive when the block’s SLEEP_EN signal is asserted.

When the block returns from sleep, if enabled, the Free Running Timer Register value will continue counting from where

it was when the block entered the Sleep state.

14.8

Description

The Input Capture and Compare Timer block has ICT Channels inputs and these can be connected to any of the 6 Cap-

ture Compare timer

Note:

The CCT0 to CCT5 blocks are expanded and shown in FIGURE 14-2: “Capture and Compare Timer

Block Diagram”

FIGURE 14-2:

CAPTURE AND COMPARE TIMER BLOCK DIAGRAM

Filter

Edge

Filter

Edge

Filter

Edge

Filter

Edge

Filter

Edge

Filter

Edge

Capture0

Timer

Capture1

Capture2

Capture3

Capture4

Capture5

CAPTURE 0

CAPTURE 1

CAPTURE 2

CAPTURE 3

CAPTURE 4

CAPTURE 5

Compare0

Compare1

COMPARE 0

COMPARE 1

CAPTURE_TIMER

TCLK Scaler

System Clock

CTOUT0

CTOUT1

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