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CS47L35 Datasheet(PDF) 293 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 293 Page - Cirrus Logic

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background image
DS1085F3
293
CS47L35
6 Register Map
R548860
(85FFCh)
DSP1_PMEM_12286
DSP1_PM_8190 [15:0]
00000000h
0
0
0
000
00
DSP1_PM_END [39:32]
R548862
(85FFEh)
DSP1_PMEM_12287
DSP1_PM_END [31:16]
00000000h
DSP1_PM_END [15:0]
R655360
(A0000h)
DSP1_XMEM_0
0
0
0
0
0
0
0
0
DSP1_XM_START [23:16]
00000000h
DSP1_XM_START [15:0]
R655362
(A0002h)
DSP1_XMEM_1
0
0
0
000
00
DSP1_XM_1 [23:16]
00000000h
DSP1_XM_1 [15:0]
R688124
(A7FFCh)
DSP1_XMEM_16382
0
0
0
0
0
0
0
0
DSP1_XM_16382 [23:16]
00000000h
DSP1_XM_16382 [15:0]
R688126
(A7FFEh)
DSP1_XMEM_16383
0
0
0
000
00
DSP1_XM_END [23:16]
00000000h
DSP1_XM_END [15:0]
R786432
(C0000h)
DSP1_YMEM_0
0
0
0
0
0
0
0
0
DSP1_YM_START [23:16]
00000000h
DSP1_YM_START [15:0]
R786434
(C0002h)
DSP1_YMEM_1
0
0
0
000
00
DSP1_YM_1 [23:16]
00000000h
DSP1_YM_1 [15:0]
R794620
(C1FFCh)
DSP1_YMEM_4094
0
0
0
0
0
0
0
0
DSP1_YM_4094 [23:16]
00000000h
DSP1_YM_4094 [15:0]
R794622
(C1FFEh)
DSP1_YMEM_4095
0
0
0
000
00
DSP1_YM_END [23:16]
00000000h
DSP1_YM_END [15:0]
R917504
(E0000h)
DSP1_ZMEM_0
0
0
0
0
0
0
0
0
DSP1_ZM_START [23:16]
00000000h
DSP1_ZM_START [15:0]
R917506
(E0002h)
DSP1_ZMEM_1
0
0
0
0
0
0
0
0
DSP1_ZM_1 [23:16]
00000000h
DSP1_ZM_1 [15:0]
R925692
(E1FFCh)
DSP1_ZMEM_4094
0
0
0
000
00
DSP1_ZM_4094 [23:16]
00000000h
DSP1_ZM_4094 [15:0]
R925694
(E1FFEh)
DSP1_ZMEM_4095
0
0
0
000
00
DSP1_ZM_END [23:16]
00000000h
DSP1_ZM_END [15:0]
R1048064
(FFE00h)
DSP1_Config_1
0
0
0
000
000
00
00
DSP1_CLK_SEL [2:0]
00000000h
0
DSP1_RATE [3:0]
0
0
0
0
0
0
DSP1_
MEM_ENA
DSP1_
DBG_
CLK_ENA
0DSP1_
CORE_
ENA
DSP1_
START
R1048068
(FFE04h)
DSP1_Status_1
DSP1_
PING_
FULL
DSP1_
PONG_
FULL
0
0
0
0
0
0
DSP1_WDMA_ACTIVE_CHANNELS [7:0]
00000000h
0
0
0
000
000
00
000
00
R1048070
(FFE06h)
DSP1_Status_2
DSP1_DUALMEM_COLLISION_ADDR [15:0]
00000000h
0
0
0
000
000
00
0
DSP1_CLK_SEL_STS [2:0]
DSP1_
CLK_
AVAIL
R1048080
(FFE10h)
DSP1_WDMA_Buffer_1
DSP1_START_ADDRESS_WDMA_BUFFER_1 [15:0]
00000000h
DSP1_START_ADDRESS_WDMA_BUFFER_0 [15:0]
R1048082
(FFE12h)
DSP1_WDMA_Buffer_2
DSP1_START_ADDRESS_WDMA_BUFFER_3 [15:0]
00000000h
DSP1_START_ADDRESS_WDMA_BUFFER_2 [15:0]
R1048084
(FFE14h)
DSP1_WDMA_Buffer_3
DSP1_START_ADDRESS_WDMA_BUFFER_5 [15:0]
00000000h
DSP1_START_ADDRESS_WDMA_BUFFER_4 [15:0]
R1048086
(FFE16h)
DSP1_WDMA_Buffer_4
DSP1_START_ADDRESS_WDMA_BUFFER_7 [15:0]
00000000h
DSP1_START_ADDRESS_WDMA_BUFFER_6 [15:0]
R1048096
(FFE20h)
DSP1_RDMA_Buffer_1
DSP1_START_ADDRESS_RDMA_BUFFER_1 [15:0]
00000000h
DSP1_START_ADDRESS_RDMA_BUFFER_0 [15:0]
R1048098
(FFE22h)
DSP1_RDMA_Buffer_2
DSP1_START_ADDRESS_RDMA_BUFFER_3 [15:0]
00000000h
DSP1_START_ADDRESS_RDMA_BUFFER_2 [15:0]
R1048100
(FFE24h)
DSP1_RDMA_Buffer_3
DSP1_START_ADDRESS_RDMA_BUFFER_5 [15:0]
00000000h
DSP1_START_ADDRESS_RDMA_BUFFER_4 [15:0]
R1048112
(FFE30h)
DSP1_DMA_Config_1
0
0
0
0
0
0
0
0
DSP1_WDMA_CHANNEL_ENABLE [7:0]
00000000h
0
0
DSP1_DMA_BUFFER_LENGTH [13:0]
R1048114
(FFE32h)
DSP1_DMA_Config_2
0
0
0
000
000
00
000
00
00000000h
0
0
0
0
0
0
0
0
DSP1_WDMA_CHANNEL_OFFSET [7:0]
R1048116
(FFE34h)
DSP1_DMA_Config_3
0
0
0
0
0
0
0
0
0
0
DSP1_RDMA_CHANNEL_OFFSET [5:0]
00000000h
0
0
0
000
000
0
DSP1_RDMA_CHANNEL_ENABLE [5:0]
R1048118
(FFE36h)
DSP1_DMA_Config_4
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
000
0
DSP1_
DMA_
WORD_
SEL
R1048120
(FFE38h)
DSP1_External_Start
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
DSP1_START_IN_SEL [4:0]
R1048128
(FFE40h)
DSP1_Scratch_1
DSP1_SCRATCH_1 [15:0]
00000000h
DSP1_SCRATCH_0 [15:0]
R1048130
(FFE42h)
DSP1_Scratch_2
DSP1_SCRATCH_3 [15:0]
00000000h
DSP1_SCRATCH_2 [15:0]
R1048146
(FFE52h)
DSP1_Bus_Error_Addr
DSP1_BUS_ERROR_ADDR_HI [15:0]
00000000h
DSP1_BUS_ERROR_ADDR_LOW [15:0]
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
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