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DS0128 Datasheet(PDF) 104 Page - Microsemi Corporation |
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DS0128 Datasheet(HTML) 104 Page - Microsemi Corporation |
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104 / 140 page  IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 94 2.3.13 Programming Times The following tables list the programming times in typical conditions when TJ = 25 °C, VDD = 1.2 V. External SPI flash part# AT25DF641-s3H is used during this measurement. Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.83 0.98 ns Read synchronous reset setup time TSRSTSU 0.271 0.319 ns Read synchronous reset hold time TSRSTHD 0.061 0.071 ns Write clock period TCCY 44 ns Write clock minimum pulse width high TCCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low TCCLKMPWL 1.8 1.8 ns Write block setup time TBLKCSU 0.404 0.476 ns Write block hold time TBLKCHD 0.007 0.008 ns Write input data setup time TDINCSU 0.003 0.004 ns Write input data hold time TDINCHD 0.137 0.161 ns Write address setup time TADDRCSU 0.088 0.104 ns Write address hold time TADDRCHD 0.247 0.29 ns Write enable setup time TWECSU 0.397 0.467 ns Write enable hold time TWECHD –0.03 –0.03 ns Maximum frequency FMAX 250 250 MHz Table 244 • JTAG Programming (Fabric Only) M2S/M2GL Device Image size Bytes Program Verify Unit 005 302672 22 10 Sec 010 568784 28 18 Sec 025 1223504 51 26 Sec 050 2424832 66 54 Sec 060 2418896 77 54 Sec 090 3645968 113 126 Sec 150 6139184 155 193 Sec Table 243 • µSRAM (RAM1024x1) in 1024 × 1 Mode (continued) Parameter Symbol –1 –Std Unit Min Max Min Max |
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