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CLRC663 Datasheet(PDF) 171 Page - NXP Semiconductors

Part # CLRC663
Description  High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
PDF  177 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CLRC663 Datasheet(HTML) 171 Page - NXP Semiconductors

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NXP Semiconductors
CLRC663
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Tables
Tab. 1.
Quick reference data CLRC66301 and
CLRC66302 .......................................................5
Tab. 2.
Quick reference data CLRC66303 .................... 5
Tab. 3.
Ordering information ..........................................6
Tab. 4.
Pin description ...................................................8
Tab. 5.
Pin description VFBGA36 ................................. 9
Tab. 6.
Interrupt sources ............................................. 12
Tab. 7.
Communication overview for ISO/IEC
14443 type A and read/write mode for
MIFARE Classic .............................................. 15
Tab. 8.
Communication overview for ISO/IEC
14443 B reader/writer ......................................16
Tab. 9.
Communication overview for FeliCa reader/
writer ................................................................17
Tab. 10. FeliCa framing and coding .............................. 18
Tab. 11. Communication overview for ISO/IEC
15693 reader/writer reader to label ................. 18
Tab. 12. Communication overview for ISO/IEC
15693 reader/writer label to reader ................. 18
Tab. 13. Communication overview for EPC/UID ............19
Tab. 14. Communication overview for Passive
communication mode ...................................... 20
Tab. 15. Framing and coding overview ......................... 20
Tab. 16. Connection scheme for detecting the
different interface types ...................................22
Tab. 17. Byte Order for MOSI and MISO ...................... 23
Tab. 18. Byte Order for MOSI and MISO ...................... 23
Tab. 19. Address byte 0 register; address MOSI ...........23
Tab. 20. Timing conditions SPI ..................................... 23
Tab. 21. Settings of BR_T0 and BR_T1 ........................24
Tab. 22. Selectable transfer speeds ..............................25
Tab. 23. UART framing ................................................. 25
Tab. 24. Byte Order to Read Data ................................ 25
Tab. 25. Byte Order to Write Data ................................ 26
Tab. 26. Timing parameter I2CL ................................... 30
Tab. 27. SPI SAM connection ....................................... 32
Tab. 28. Boundary scan command ............................... 32
Tab. 29. Boundary scan path of the CLRC663 ..............34
Tab. 30. Settings for TX1 and TX2 ............................... 39
Tab. 31. Setting residual carrier and modulation
index by TXamp.set_residual_carrier .............. 39
Tab. 32. Configuration for single or differential
receiver ............................................................42
Tab. 33. Register configuration of CLRC663 active
antenna concept (DIGITAL) .............................43
Tab. 34. Register configuration of CLRC663 active
antenna concept (Antenna) .............................43
Tab. 35. EEPROM memory organization ...................... 45
Tab. 36. Production area (Page 0) ................................46
Tab. 37. Product ID overview of CLRC663 family ......... 46
Tab. 38. Configuration area (Page 0) ............................47
Tab. 39. Interface byte .................................................. 47
Tab. 40. Interface bits ....................................................47
Tab. 41. Tx and Rx arrangements in the register set
protocol area ................................................... 48
Tab. 42. Register reset values (Hex.) (Page0) .............. 48
Tab. 43. Register reset values (Hex.)(Page1 and
page 2) ............................................................49
Tab. 44. Crystal requirements recommendations ..........50
Tab. 45. Divider values for selected frequencies
using the integerN PLL ................................... 51
Tab. 46. Command set ..................................................53
Tab. 47. Predefined protocol overview RX ....................57
Tab. 48. Predefined protocol overview TX .................... 57
Tab. 49. Behavior of register bits and their
designation ...................................................... 60
Tab. 50. CLRC663 registers overview ...........................60
Tab. 51. Command register (address 00h) ....................63
Tab. 52. Command bits ................................................. 63
Tab. 53. HostCtrl register (address 01h); ...................... 63
Tab. 54. HostCtrl bits .....................................................64
Tab. 55. FIFOControl register (address 02h); ............... 64
Tab. 56. FIFOControl bits ..............................................64
Tab. 57. WaterLevel register (address 03h); ................. 65
Tab. 58. WaterLevel bits ................................................65
Tab. 59. FIFOLength register (address 04h); reset
value: 00h ........................................................65
Tab. 60. FIFOLength bits .............................................. 65
Tab. 61. FIFOData register (address 05h); ................... 66
Tab. 62. FIFOData bits ..................................................66
Tab. 63. IRQ0 register (address 06h); reset value:
00h .................................................................. 66
Tab. 64. IRQ0 bits ......................................................... 66
Tab. 65. IRQ1 register (address 07h) ............................67
Tab. 66. IRQ1 bits ......................................................... 67
Tab. 67. IRQ0En register (address 08h) ....................... 68
Tab. 68. IRQ0En bits .....................................................68
Tab. 69. IRQ1EN register (address 09h); ......................68
Tab. 70. IRQ1EN bits .................................................... 68
Tab. 71. Error register (address 0Ah) ............................69
Tab. 72. Error bits ..........................................................69
Tab. 73. Status register (address 0Bh) ......................... 70
Tab. 74. Status bits ....................................................... 70
Tab. 75. RxBitCtrl register (address 0Ch); .................... 71
Tab. 76. RxBitCtrl bits ................................................... 71
Tab. 77. RxColl register (address 0Dh); ........................71
Tab. 78. RxColl bits .......................................................71
Tab. 79. TControl register (address 0Eh) ......................72
Tab. 80. TControl bits ....................................................72
Tab. 81. T0Control register (address 0Fh); ................... 73
Tab. 82. T0Control bits ..................................................73
Tab. 83. T0ReloadHi register (address 10h); ................ 73
Tab. 84. T0ReloadHi bits ...............................................73
Tab. 85. T0ReloadLo register (address 11h); ................74
Tab. 86. T0ReloadLo bits .............................................. 74
Tab. 87. T0CounterValHi register (address 12h) ........... 74
Tab. 88. T0CounterValHi bits ........................................ 74
Tab. 89. T0CounterValLo register (address 13h) .......... 74
Tab. 90. T0CounterValLo bits ........................................74
Tab. 91. T1Control register (address 14h); ................... 75
Tab. 92. T1Control bits ..................................................75
Tab. 93. T0ReloadHi register (address 15h) ................. 75
CLRC663
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.3 — 3 January 2024
171 / 177



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