CLRC663 datasheet(175/177 Pages) NXP

175 / 177 page

NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Contents

General description .........................................1

Features and benefits ..................................... 3

Applications ..................................................... 4

Quick reference data .......................................5

Ordering information .......................................6

Block diagram ..................................................7

Pinning information .........................................8

7.1

Pin description HVQFN32 ................................. 8

7.2

Pin description VFBGA36 ..................................9

Functional description .................................. 11

8.1

Interrupt controller ............................................11

8.2

Timer module ...................................................12

8.2.1

Timer modes ....................................................14

8.2.1.1

Time-Out- and Watch-Dog-Counter ................. 14

8.2.1.2

Wake-up timer ................................................. 14

8.2.1.3

Stop watch .......................................................14

8.2.1.4

Programmable one-shot timer ......................... 14

8.2.1.5

Periodical trigger ..............................................14

8.3

Contactless interface unit ................................ 14

8.3.1

Communication mode for ISO/IEC 14443

type A and for MIFARE Classic ....................... 15

8.3.2

ISO/IEC14443 type B functionality .................. 16

8.3.3

FeliCa functionality .......................................... 17

8.3.3.1

FeliCa framing and coding .............................. 18

8.3.4

ISO/IEC15693 functionality ..............................18

8.3.5

EPC-UID/UID-OTP functionality ...................... 19

8.3.6

ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

functionality ......................................................19

8.3.6.1

Data encoding ICODE .....................................19

8.3.7

ISO/IEC 18092 mode ...................................... 20

8.3.7.1

Passive communication mode .........................20

8.3.7.2

ISO/IEC 18092 framing and coding .................20

8.3.7.3

ISO/IEC 18092 protocol support ......................21

8.4

Host interfaces .................................................22

8.4.1

Host interface configuration .............................22

8.4.2

SPI interface .................................................... 22

8.4.2.1

General ............................................................ 22

8.4.2.2

Read data ........................................................23

8.4.2.3

Write data ........................................................ 23

8.4.2.4

Address byte ....................................................23

8.4.2.5

Timing Specification SPI ..................................23

8.4.3

RS232 interface ...............................................24

8.4.3.1

Selection of the transfer speeds ......................24

8.4.3.2

Framing ............................................................25

8.4.4

I2C-bus interface ............................................. 26

8.4.4.1

General ............................................................ 26

8.4.4.2

I2C Data validity .............................................. 27

8.4.4.3

I2C START and STOP conditions ....................27

8.4.4.4

I2C byte format ................................................28

8.4.4.5

I2C Acknowledge .............................................28

8.4.4.6

I2C 7-bit addressing ........................................ 29

8.4.4.7

I2C-register write access ................................. 29

8.4.4.8

I2C-register read access ................................. 29

8.4.4.9

I2CL-bus interface ........................................... 30

8.4.5

SAM interface .................................................. 31

8.4.5.1

SAM functionality .............................................31

8.4.5.2

SAM connection .............................................. 32

8.4.6

Boundary scan interface ..................................32

8.4.6.1

Interface signals .............................................. 33

8.4.6.2

Test Clock (TCK) ............................................. 33

8.4.6.3

Test Mode Select (TMS) ..................................33

8.4.6.4

Test Data Input (TDI) .......................................33

8.4.6.5

Test Data Output (TDO) .................................. 34

8.4.6.6

Data register .................................................... 34

8.4.6.7

Boundary scan cell .......................................... 34

8.4.6.8

Boundary scan path ........................................ 34

8.4.6.9

Boundary Scan Description Language

(BSDL) ............................................................. 35

8.4.6.10 Non-IEEE1149.1 commands ............................36

8.5

Buffer ............................................................... 36

8.5.1

Overview ..........................................................36

8.5.2

Accessing the FIFO buffer ...............................36

8.5.3

Controlling the FIFO buffer ..............................36

8.5.4

Status Information about the FIFO buffer .........36

8.6

Analog interface and contactless UART .......... 38

8.6.1

General ............................................................ 38

8.6.2

TX transmitter .................................................. 38

8.6.2.1

Overshoot protection ....................................... 40

8.6.2.2

Bit generator .................................................... 41

8.6.3

Receiver circuitry ............................................. 41

8.6.3.1

General ............................................................ 41

8.6.3.2

Block diagram ..................................................41

8.6.4

Active antenna concept ................................... 42

8.6.5

Symbol generator ............................................ 45

8.7

Memory ............................................................45

8.7.1

Memory overview .............................................45

8.7.2

EEPROM memory organization .......................45

8.7.2.1

Product information and configuration -

Page 0 ............................................................. 46

8.7.3

EEPROM initialization content

LoadProtocol ....................................................48

8.8

Clock generation ..............................................50

8.8.1

Crystal oscillator .............................................. 50

8.8.2

IntegerN PLL clock line ................................... 50

8.8.3

Low Frequency Oscillator (LFO) ......................51

8.9

Power management .........................................51

8.9.1

Supply concept ................................................ 51

8.9.2

Power reduction mode .....................................52

8.9.2.1

Power-down .....................................................52

8.9.2.2

Standby mode ................................................. 52

8.9.2.3

Modem off mode ............................................. 52

8.9.3

Low-Power Card Detection (LPCD) .................52

8.9.4

Reset and start-up time ...................................53

8.10

Command set .................................................. 53

8.10.1

General ............................................................ 53

8.10.2

Command set overview ...................................53

8.10.3

Command functionality .................................... 54

8.10.3.1 Idle command .................................................. 54

8.10.3.2 LPCD command .............................................. 54

8.10.3.3 Load key command ......................................... 54

8.10.3.4 MFAuthent command .......................................55

8.10.3.5 AckReq command ........................................... 55

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

175 / 177

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