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CLRC663 Datasheet(PDF) 119 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 119 Page - NXP Semiconductors |
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119 / 177 page  NXP Semiconductors CLRC663 High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus Symbol Parameter Conditions Min Typ Max Unit CL external buffer capacitor AVDD 220 470 - nF CL external buffer capacitor DVDD 220 470 - nF I/O pin characteristics SIGIN/OUT7, SIGOUT, CLKOUT/OUT6, IFSEL0/OUT4, IFSEL1/OUT5, TCK/OUT3, TMS/OUT2, TDI/ OUT1, TDO/OUT0, IRQ, IF0, IF1, IF2, SCL2, SDA2 ILI input leakage current output disabled 0.0 50 500 nA VIL low-level input voltage -0.5 - 0.3 x VDD(PVDD) V VIH high-level input voltage 0.7 x VDD(PVDD) VDD(PVDD)VDD(PVDD) + 0.5 V VOL low-level output voltage 0.0 0.0 0.4 V VOH high-level output voltage If pins are used as output OUTx, IOH = 4 mA driving current for each pin VDD(PVDD)-0.4 VDD(PVDD)VDD(PVDD) V Ci input capacitance 0.0 2.5 4.5 pF Pin characteristics PDOWN VIL low-level input voltage 0.0 0.0 0.4 V VIH high-level input voltage 0.6 x VPVDD VDD(PVDD)VDD(PVDD) V Pull-up resistance for TCK, TMS, TDI, IF2 Rpu pull-up resistance 50 72 120 KΩ Pin characteristics AUX 1, AUX 2 Vo output voltage 0.0 - 1.8 V CL load capacitance 0.0 - 400 pF Pin characteristics RXP, RXN Vi(p) input voltage 0 1.65 1.8 V Ci input capacitance 2 3.5 5 pF Vmod(pp) modulation voltage Vmod(pp) = Vi(pp)(max) - Vi(pp) (min) - 2.5 - mV Pins TX1 and TX2 Vo output voltage Vss(TVSS) - VDD(TVDD) V CLRC66301, CLRC66302: T=25°C, VDD(TVDD) = 5.0V - 1.5 - Ω Ro output resistance CLRC66303: T=25°C, VDD(TVDD) = 5.0V - 1.2 - Ω Clock frequency Pin CLKOUT fclk clock frequency configured to 27.12 MHz - 27.12 - MHz δclk clock duty cycle - 50 - % Crystal connection XTAL1, XTAL2 Vo(p-p) peak-to-peak output voltage pin XTAL1 - 1.0 - V Table 254. Characteristics...continued CLRC663 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5.3 — 3 January 2024 119 / 177 |
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