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CLRC663 Datasheet(PDF) 121 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 121 Page - NXP Semiconductors |
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121 / 177 page  NXP Semiconductors CLRC663 High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus 001aak012 VMID 0 V Vmod Vi(p-p)(max) Vi(p-p)(min) 13.56 MHz carrier Figure 34. Pin RX input voltage 13.1 Timing characteristics Symbol Parameter Conditions Min Typ Max Unit tSCKL SCK LOW time 50 - - ns tSCKH SCK HIGH time 50 - - ns th(SCKH-D) SCK HIGH to data input hold time SCK to changing MOSI 25 - - ns tsu(D-SCKH) data input to SCK HIGH set-up time changing MOSI to SCK 25 - - ns th(SCKL-Q) SCK LOW to data output hold time SCK to changing MISO - - 25 ns t(SCKL-NSSH) SCK LOW to NSS HIGH time 0 - - ns tNSSH NSS HIGH time before communication 50 - - ns Table 255. SPI timing characteristics Remark: To send more bytes in one data stream, the NSS signal must be LOW during the send process. To send more than one data stream, the NSS signal must be HIGH between each data stream. Fast mode Fast mode Plus Symbol Parameter Conditions Min Max Min Max Unit fSCL SCL clock frequency 0 400 0 1000 kHz tHD;STA hold time (repeated) START condition after this period, the first clock pulse is generated 600 - 260 - ns tSU;STA set-up time for a repeated START condition 600 - 260 - ns tSU;STO set-up time for STOP condition 600 - 260 - ns tLOW LOW period of the SCL clock 1300 - 500 - ns tHIGH HIGH period of the SCL clock 600 - 260 - ns tHD;DAT data hold time 0 900 - 450 ns tSU;DAT data set-up time 100 - - - ns tr rise time SCL signal 20 300 - 120 ns tf fall time SCL signal 20 300 - 120 ns tr rise time SDA and SCL signals 20 300 - 120 ns Table 256. I2C-bus timing in fast mode and fast mode plus CLRC663 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5.3 — 3 January 2024 121 / 177 |
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