VNF9D5F datasheet(8/106 Pages) STMICROELECTRONICS

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Operating mode

Entering conditions

Leaving conditions

Characteristics

1st communication frame:

• UNLOCK bit = 1 AND EN bit =1

2nd communication frame:

• GOSTBY bit = 1 AND EN bit = 0

This procedure avoids entering

the pre-standby mode

unintentionally.

• Harness protection: available for all channels.

The channels are configured in latch mode;

• Reset bit = 0

• Regular toggling of WDTB is necessary within

timeout period tWDTB

Pre-standby mode

• If it is in fail-safe mode AND

STDBY_NOT low AND (CSN high

OR VDD < VDD_TH) for a time t >

tprestdby

• If it is in normal mode AND the

SPI sends the following

sequence:

1st communication frame:

• UNLOCK = 1 AND EN = 1

2nd communication frame:

• GOSTBY = 1 AND EN = 0

(It is recommended to set also

UNLOCK = 0, in this second

frame). This procedure avoids

entering the pre-standby mode

unintentionally.

To fail-safe mode:

If STDBY_NOT = 1 OR (CSN low

and VDD > VDD_TH)

To standby mode:

If STDBY_NOT = 0 AND (CSN

high or VDD < VDD_TH) AND all I²t

counters = 0 and tstdby elapsed

To sleep mode:

VREG < VREG_POR_L

• Outputs: OFF

• SPI: active

• Diagnostic: available

• Registers: read/write is allowed

• Protections: active

• I²t counters decreasing and tstdby timer running

Capacitive

charging mode

(CCM): this is not

device operating

mode, but channel

specific operating

mode

From fail-safe mode:

• If MCUext = 1 AND after 5

consecutive rising edges on DIx

pins within tCCM_EN, the

corresponding channels will enter

CCM, according to DIx OTP

configuration.

• If MCUext = 0 AND after 5

consecutive rising edges on DI1

pin within tCCM_EN, according to

OTP programming, relevant

channels will enter CCM.

From normal mode:

• Set CAPCRx bit in SOCR

• Automatically after tCCM_DIS time

frame in both fail-safe and normal

states.

• In normal mode, also through a

SPI frame, setting EXIT_CAPCRx

bit in SOCR register whenever

within tCCM_DIS time frame

• Harness protections: disabled

• LED mode: disabled

• SPI: active

• Latch-OFF delay time (tD_RESTART) after TSD

event is disabled

• Related parameters reported in Table 67

Battery

undervoltage:

transition phase

(not device

operating mode)

Any mode: VCC < VUSD

If VDD present AND

VREG > VREG_POR_H

• Digital current-sense diagnostic:

not available

• Output stages are off regardless SPI or DIx

status

• SPI: active

• Diagnostic: available

• Registers: reading is possible

• VCCUV flag set, SPI registers content retained

If VCC > VUSD + VUSDhyst, the device comes

back to the last mode and the VCCUV flag is

cleared.

If VREG < VREG_POR_L during VCC increasing,

the device is reset: the last operation mode is

lost, the logic part is unpowered and the device

enters Standby mode as soon as VCC > VUSD +

VUSDhyst.

VNF9D5F

Functional description

DS13946 - Rev 6

page 8/106

VNF9D5F Datasheet(PDF) 8 Page - STMicroelectronics

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