VNF9D5F datasheet(21/106 Pages) STMICROELECTRONICS

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SPI functional description

4.1

SPI communication

The SPI communication is based on a standard ST-SPI 24-bit interface, using CSN, SDI, SDO and SCK signal

lines.

Input data are shifted into SDI, MSB first while output data are shifted out on SDO, MSB first.

4.1.1

Signal description

During all operations, VDD must be held stable and within the specified valid range: VDD min to VDD max. The

VREG must be held stable and within the specified range, VREG min to VREG max, to supply the digital part.

Table 13. SPI signal description

Name

Function

Serial

clock

SCK

This input signal provides the timing of the serial interface. Data present at serial data input (SDI) are latched on

the rising edge of the serial clock (SCK). Data on serial data output (SDO) change after the falling edge of the

serial clock (SCK freq > 1 MHz).

Serial

data input

SDI

This input signal is used to transfer data serially into the device. It receives data to be written. Values are sampled

on the rising edge of the serial clock (SCK).

Serial

data

output

SDO

This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of the

serial clock (SCK).

Chip

select

CSN

When this input signal is high, the device is deselected and serial data output (SDO) is high-Z. Driving this input

Low enables the communication. The communication must start on a Low level of serial clock (SCK). Data are

accepted only if exactly 24 bits have been shifted in.

Note:

As per the ST_SPI standard, in the case of failing communication:

•

CSN stuck at HIGH:

–

If the device is in normal mode, a WDTB timeout forces the device into fail-safe

mode. The serial data out (SDO) remains in high impedance (high-Z). Any valid

communication arrived after this event is accepted by the device.

•

CSN stuck at LOW:

–

In this case and whatever the mode of the device, a CSN timeout protection is

activated and force the device to release the SPI bus. Then the serial data out

(SDO) will go into high impedance (high-Z)

A reset of the CSN timeout (see tSHCH in Table 51) is activated with a transition Low to high on the CSN pin (or

with a power on reset or software reset). With this reset, the serial data out (SDO) is released and any valid

communication is accepted by the device. Without this reset, the next communication is not considered by the

device.

4.1.2

Connecting to the SPI bus

A schematic view of the architecture between the bus and devices can be seen in the Figure 15.

All input data bytes are shifted into the device, MSB first. The serial data input (SDI) is sampled on the first rising

edge of the serial clock (SCK) after chip select (CSN) goes low. All output data bytes are shifted out of the device

on the falling edge of SCK, MSB first on the first falling edge of the chip select (CSN).

VNF9D5F

SPI functional description

DS13946 - Rev 6

page 21/106

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