VNF9D5F datasheet(4/106 Pages) STMICROELECTRONICS

4 / 106 page

Table 1. Pin functionality description

Pin #

Name

Function

TAB

VCC

Battery connection: this is the backside TAB and is the direct connection to drain Power MOSFET

switches. It is also used for the connection to the drain of the external Power MOSFET used for

reverse battery protection.

5, 20

N.C.

Not connected pin.

6-8, 25-32

N.C.

Not connected pin.

Note:

To improve device thermal performances, these not connected leads can be

soldered to VCC, upon creating solder masks around each lead. This precaution

is needed since a unique soldering plate for TAB, leads 6-8 and leads 25-32

could end up with solder displacement.

9, 10

DI0, DI1

Direct input: direct control for OUTx in limp-home mode. Configurable as OR combination with the

relevant SPI OUTx control bit in normal mode.

PWM_CLK

External clock of PWM engine.

CSN

Chip select not (active low): it is the selection pin of the device. It is a CMOS compatible input.

SCK

Serial clock: it is a CMOS compatible input.

SDI

Serial data input: transfers data to be written serially into the device on the SCK rising edge.

SDO

Serial data output: transfers data serially out of the device on the SCK falling edge.

VDD

DC supply input for the SPI interface. 3.3 V and 5 V compatible.

GND

Ground connection: this pin serves as the ground connection for the logic part of the device.

VREG

DC output of internal preregulator (4.7 V) generated from VCC to supply VREG pin and digital

control circuit.

Connect a low ESR capacitor (2 μF) in series with a resistor (120 Ω) close to this pin referenced to

device ground.

STDBY_NOT Standby mode enabler (active Low).

1-4

OUTPUT1

Power OUTPUT 1: direct connection to the source Power MOSFET channel 1.

21-24

OUTPUT0

Power OUTPUT 0: direct connection to the source Power MOSFET channel 0.

VNF9D5F

Block diagram and pin description

DS13946 - Rev 6

page 4/106

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