VNF9D5F datasheet(31/106 Pages) STMICROELECTRONICS

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The duty cycle of the output signal is configured for each OUTPUTX with the OUTCTRCR register using 10 bits

(MSB first):

•

Programming an output duty cycle at 000h will result in a 0% duty cycle, it means channel always OFF

depending on the SOCR/DIx bit setting.

•

Programming an output duty cycle at 3FFh will result in a 100% duty cycle (4095/4096), it means channel

always ON when the SOCR/DIx bit is set.

–

In normal mode the outputs are driven according to the SPI register setting and INx pins (DIx in OR

with SPI) if the related DIENCR bit is set.

Set PWMSYNC bit in Control Register “CTRL” (to synchronize internal PWM counter to the selected channels).

The internal PWM counter is 12 bits depth, it is active whatever the state of the channels, if VDD >

VDD_POR_ON.

The set of PWMSYNC bit allows to reset the PWM counter.

The phase shift of the output signal is configured for each OUTPUTx by internally concatenating the CHPHAx 5

bits with '00000' in order to get 10 bits (5 bits + 0000). Granularity of the phase shift is 5 bits. CHPHA = 00000b

means a phase shift of 0 (internal 10bit phase shift is 0x000=0000000000b), while CHPHA = 11111b results in a

maximum phase shift of 31/32 = (internal 10bit phase shift is 0x3E0 = 0000000000b). The phase shift is relative to

the base frequency of the selected channel. Thus, the exact point in time when the channel switches on also

depends on the operating mode of the selected channel.

Table 32. Phase shift configuration

Phase Shift (%)

5 Bits

10 Bits

Phase Shift (ms)

PWM = 400 kHz

Divider = 2048

Phase Shift (ms)

PWM = 400 kHz

Divider = 1024

Phase Shift (ms)

PWM = 400 kHz

Divider = 512

9.4

0.481

0.24

0.12

28.1

120

1.439

0.719

0.360

46.9

1E0

2.40

1.2

0.6

2E0

3.84

1.92

0.96

380

4.608

2.304

1.152

A change of phase/duty will be taken in account after the next zero crossing of the PWM counter.

Note:

If the frequency on PWMCLK is too low (f < PWM_Clk), the device falls back to an internally generated PWM

frequency of approximately 400 kHz. In this case the PWMCLOCKLOW bit in the OUTSRx and the global error

flag are set.

4.4.1

OTP programming

A dedicated OTP manages the direct input configuration. A corresponding bit named “MCUext” is stored in a

MCUext = 1 (default)

Table 33. OTP memory map - MCUext = 1

OTP Memory Map Register (3Eh)

bit 1, bit 0

CH1

N.A.

DI1

OFF

CH0

DI0

DI1

OFF

In fail-safe mode, the device is configured in auto restart in case of harness protection triggering (automatic

restart will occur when Counter down count will reach 0). ITOFFSRx will be set as soon as harness protection is

triggered, it can be reset only by a R&C command (unlatching the channel, no counter reset).

VNF9D5F

SPI functional description

DS13946 - Rev 6

page 31/106

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