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VNF9D5F Datasheet(PDF) 22 Page - STMicroelectronics |
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VNF9D5F Datasheet(HTML) 22 Page - STMicroelectronics |
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22 / 106 page  4.1.3 SPI mode Supported SPI mode during a communication phase can be seen in the following figure: Figure 14. Supported SPI mode µC SPI Master VNF9D5F Slave CSN SCK SDI SDO MSB MSB LSB LSB CSN SCK SDI SDO This device can be driven by a micro controller with its SPI peripheral running in the following mode: • CPOL = 0, CPHA = 0 Figure 15. Bus master and two devices in a normal configuration BUS master SPI interface with CPOL = 0 CPHA = 0 CS1 CS2 VNF9D5F CSN2 CSN1 SCK SDI SDO SCK SDI SDO VNF9D5F 4.2 SPI protocol 4.2.1 SDI, SDO format SDI format during each communication frame starts with a command byte. It begins with two bits of operating code (OC0, OC1) which specify the type of operation (read, write, read and clear status, read device information) and it is followed by a 6-bit address (A0:A5). The command byte is followed by two input data bytes (D15:D8) and (D7:D0). VNF9D5F SPI functional description DS13946 - Rev 6 page 22/106 |
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