VNF9D5F datasheet(23/106 Pages) STMICROELECTRONICS

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Table 14. Command byte

MSB

LSB

OC1

OC0

Table 15. Input data byte 1

MSB

LSB

D15

D14

D13

D12

D11

D10

Table 16. Input data byte 2

MSB

LSB

D0(1)

1. D0 is the parity bit.

SDO format during each communication frame starts with a specific byte called Global Status Byte (see GSB byte

for more details of bit0-bit7). This byte is followed by two output data bytes (D15:D8) and (D7:D0).

Table 17. Global status byte

MSB

LSB

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Table 18. Output data byte 1

MSB

LSB

D15

D14

D13

D12

D11

D10

Table 19. Output data byte 2

MSB

LSB

4.2.2

Operating code definition

The SPI interface features four different addressing modes which are listed in Table 20:

Table 20. Operating codes

OC1

OC0

Meaning

Write operation

Read operation

Read and clear status operation

Read device information

Write mode

The write mode of the device allows to write the content of the input data byte into the addressed register (see list

of registers in Table 25). Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first.

During the same sequence the outgoing data are shifted out MSB first on the falling edge of the CSN pin and the

subsequent bits on the falling edge of the serial clock (SCK). The first byte corresponds to the Global Status Byte

and the second to the previous content of the addressed register.

VNF9D5F

SPI functional description

DS13946 - Rev 6

page 23/106

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