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VNF9D5F Datasheet(PDF) 27 Page - STMicroelectronics |
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VNF9D5F Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 106 page  Bit Name Reset Content 5 SPI error (SPIE) 0 The SPIE is a logical OR combination of errors related to a wrong SPI communication (SCK count and SDI stuck at errors). The SPIE bit is automatically set when SDI is stuck at High or Low. The SPIE is automatically cleared by a valid SPI communication. 4 Thermal shutdown (TSD) or power limitation (PL) 0 This bit is set in case of thermal shutdown or power limitation. 3 I²t channel latch off (ITLOFF) 0 Logical OR combination of STi²Fuse latch for each channel. 2 Latch Off (LOFF) 0 The device error bit is set in case one or more channels are latched OFF 1 Case temperature bit (TCASE) 0 This bit is set if the frame temperature is greater than the threshold (120 ºC), it can be used as a temperature pre-warning. The bit is automatically cleared when the frame temperature drops below the case-temperature reset threshold (TCR1). (It corresponds to the content of the bit TW1) 0 Fail-safe (FS) 1 The bit is set in case device operates in Fail Safe mode. Note: The FFh or 00h combinations for the global status byte are not possible, due to the active low of global status bit (bit 7), exclusive combination exists between bit 7 and bit 0 - bit 6. Consequently, a FFh or 00h combination for the global status byte must be detected by the microcontroller as a failure (SDO stuck to GND or to VDD or loss of SCK). 4.3.2 RAM RAM registers can be separated according to the frequency of usage: • Init–register is read/written during the initialization phase (single shot action). • Continuous–read/write/read and clear registers are often accessed, applying outputs control and diagnostic. • Rare–read/read and clear status of device registers accessed on demand (in case of failure). Table 25. RAM memory map Address Name Access Content Access type Reset value Control registers 00h OUTCTRCR0 Read/Write Output control configuration register channel 0 Init 0x0000 01h OUTCTRCR1 Read/Write Output control configuration register channel 1 Init 0x0000 Not used area 08h OUTCFGR0 Read/Write Output configuration register 0 Init 0x0000 09h OUTCFGR1 Read/Write Output configuration register 1 Init 0x0000 Not used area 10h CHLOFFTCR0 Read/Write Channel latch-off timing control register 1 (channels 1, 0) Init 0x0000 Not used area 13h SOCR Read/Write Channel control register Init 0x0000 14h CTRL Read/Write Control register Init 0x0000 15h FSITCR0 Read/Write Fail-safe and I²t settings for channel 0 Init 0x0200 16h FSITCR1 Read/Write Fail-safe and I²t settings for channel 1 Init 0x0200 Not used area STATUS REGISTERS 20h OUTSR0 Read/Clear Output status register Channel 0 rare 0x0000 VNF9D5F SPI functional description DS13946 - Rev 6 page 27/106 |
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