VNF9D5F datasheet(104/106 Pages) STMICROELECTRONICS

104 / 106 page

List of figures

Figure 1.

Block diagram .................................................................... 3

Figure 2.

Connection diagram ................................................................ 3

Figure 3.

Device state diagram................................................................ 6

Figure 4.

Channel state diagram (CCM) ........................................................ 11

Figure 5.

Normal mode, short circuit - Programmable Blanking Window (PBW) > tD_RESTART .................... 12

Figure 6.

Normal mode, short circuit - Programmable Blanking Window (PBW) < tD_RESTART .................... 13

Figure 7.

Protection curve with INOM = 10 A and tNOM = 300 s vs a 0.5 mm2 wire isothermic curve ................ 16

Figure 8.

Protection curve in parallel mode with INOM = 20 A and tNOM = 300 s vs a 1.5 mm2 wire isothermic curve .... 16

Figure 9.

Lowest (left hand) and highest (right hand) INOM and tNOM configuration setting on a 1 mm2 wire .......... 17

Figure 10.

I²t counter with varying INOM latch and unlatch ............................................. 18

Figure 11.

I²t counter after POR with IOUT > INOM ................................................... 19

Figure 12.

I²t counter after POR with IOUT < INOM ................................................... 19

Figure 13.

Transition to standby mode with I²t counter running .......................................... 20

Figure 14.

Supported SPI mode ............................................................... 22

Figure 15.

Bus master and two devices in a normal configuration ........................................ 22

Figure 16.

SPI write operation ................................................................ 24

Figure 17.

SPI read operation ................................................................ 24

Figure 18.

SPI read and clear operation ......................................................... 25

Figure 19.

SPI read device information .......................................................... 25

Figure 20.

Direct input block diagram - valid for 2, 4 and 6 channels device ................................. 33

Figure 21.

ADC characteristics and error definition .................................................. 52

Figure 22.

Conversion window generation ........................................................ 53

Figure 23.

Minimum ON time for digital current sense availability ........................................ 53

Figure 24.

Channel's sequence internal stack ..................................................... 54

Figure 25.

Sequence of channels .............................................................. 55

Figure 26.

Asynchronous with continuous sampling ................................................. 56

Figure 27.

Diagnostic registers................................................................ 58

Figure 28.

Status registers .................................................................. 59

Figure 29.

Open-load OFF-state detection........................................................ 60

Figure 30.

Internal timer process .............................................................. 62

Figure 31.

One timer step actions.............................................................. 63

Figure 32.

Power limitation counter flowchart ...................................................... 64

Figure 33.

Example of behavior channel configuration ............................................... 65

Figure 34.

Current and voltage conventions....................................................... 70

Figure 35.

SPI dynamic characteristics .......................................................... 74

Figure 36.

Switching characteristics ............................................................ 81

Figure 37.

Application schematic .............................................................. 85

Figure 38.

Maximum turn off current versus inductance – Bulb mode ..................................... 87

Figure 39.

Maximum turn off current versus inductance – LED mode ..................................... 87

Figure 40.

Maximum turn off energy versus inductance – Bulb mode ..................................... 88

Figure 41.

Maximum turn off energy versus inductance – LED mode ..................................... 88

Figure 42.

QFN (6x6 mm) PCB footprint ......................................................... 89

Figure 43.

QFN (6x6 mm) PCB 2 cm2 ........................................................... 89

Figure 44.

QFN (6x6 mm) PCB 8 cm2 ........................................................... 90

Figure 45.

QFN (6x6 mm) PCB 4 layer2 ......................................................... 90

Figure 46.

RthJA vs PCB copper area in open box free air conditions ..................................... 91

Figure 47.

QFN 6x6 thermal impedance junction ambient ............................................. 92

Figure 48.

Thermal fitting model ............................................................... 92

Figure 49.

QFN (6x6 mm) package outline ....................................................... 94

Figure 50.

QFN (6x6 mm) reel 13" ............................................................. 96

Figure 51.

QFN (6x6 mm) carrier tape........................................................... 96

VNF9D5F

List of figures

DS13946 - Rev 6

page 104/106

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