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PM73121 Datasheet(PDF) 38 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 38 Page - PMC-Sierra, Inc |
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38 / 223 page ![]() PM73121 AAL1gator II PMC-Sierra, Inc. PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ occurrences of each type of event. If a count is required, the counters should be used instead. The status bits for the receive error conditions on each queue are maintained in a single-data word. When a set bit is detected, this single-data word should be cleared immediately. NOTE: As new events can occur between the read of the status bits and the write to clear the status bits, the status bits should be used for statistics gathering only. 2.6 Interrupts The AAL1gator II asserts the interrupt line whenever an OAM cell arrives and the interrupt mask is deasserted. The interrupt can be cleared by asserting OAM_INT_MASK or by asserting CLR_ RX_OAM_LATCH. Refer to section 7.9 “CMDREG (Command Register)” on page 165. 2.7 SRTS and Transmit Line Interface Clock Configurations The AAL1gator II provides the following transmit line interface clock configurations on a per-line basis: • Drives TL_CLK(i) with the looped-back RL_CLK(i). • Drives TL_CLK(i) with the SRTS-derived clock. • Drives TL_CLK(i) with a nominal T1/E1 clock of 1.544 MHz or 2.048 MHz. • Accepts TL_CLK(i) as an input. NOTE: The AAL1gator II uses Bellcore’s patented SRTS clock recovery technique. Refer to the NOTE on page 172 for additional information regarding Bellcore’s SRTS patent. The AAL1gator II also provides the following external TL_CLK generation options through the multiplexed SRTS output port. These options can be used when the AAL1gator II accepts TL_ CLK(i) as an input: • The AAL1gator II drives SRTS information out of the SRTS port. An external circuit can use this information to synthesize an SRTS-based TL_CLK. (Provided for backward compatibility with the WAC-021-C-X.) • The AAL1gator II drives adaptive clocking information out of the SRTS port. An external circuit can use this information to synthesize an adaptive (based on receive-buffer-centering) TL_CLK. 2.8 Peak Cell Rates (PCRs) For purposes of discussion, the following PCR information is assumed: • Full cells are used, • The PCR numbers are per line, and • The SYS_CLK is 38.88 MHz. 2.8.1 Peak Cell Rates (PCRs) for Structured Cell Formats • PCR ≤ 176 × n cells per second where 1 ≤ n ≤ 32 (assuming completely filled cells). |
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