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PM73121 Datasheet(PDF) 90 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 90 Page - PMC-Sierra, Inc |
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90 / 223 page  PM73121 AAL1gator II PMC-Sierra, Inc. PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ The AAL1gator II provides the receive buffer frame difference for an external circuit to generate an adaptive TL_CLK signal. The general mechanism is often termed “buffer centering”. A clock delta value is determined externally by subtracting the nominal frame difference (value of R_ CDVT) from the actual receive buffer frame difference. This delta value is then transformed into the frequency selection for an external TL_CLK frequency synthesizer. The closed-loop action of this circuit causes the delta value to find a center point. When the delta is above the center point, there is too much data buffered and the TL_CLK frequency must be increased. When the delta is below the center point, there is too little data buffered and the TL_CLK frequency must be decreased. As mentioned in the ATM Forum CES Standard Specification (refer to Appendix B, “Refer- ences”, on page 203), the adaptive clock recovery algorithm does not meet the T1/E1 clock wan- der requirements. See Figure 52, which shows a direct adaptive clocking implementation. 3 0 0 frame_diff(8) frame_diff(7) 2 frame_diff(6) frame_diff(5) frame_diff(4) frame_diff(3) 1 frame_diff(2) frame_diff(1) frame_diff(0) 0 0 0000 NOTES: • The 9-bit frame_diff value gives the number of frames currently stored in the rx frame buffer. For UDF-ML mode, frame_diff is expressed in 256-bit increments. • The cell_vci(7:5) identifies the eight line numbers. • The cell_vci(4:0) bits can be ignored in UDF-ML mode. • The frame difference values for each queue are played out in sequence 5 to 0 every time a cell is received and a valid frame difference can be calculated. Table 4. Frame Difference (Continued) SRTS_LINE(3:0) Value SRTS_DOUT(3:0) Value 3210 |
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