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PM73121 Datasheet(PDF) 83 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 83 Page - PMC-Sierra, Inc |
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83 / 223 page  PM73121 AAL1gator II PMC-Sierra, Inc. PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ uses the synchronization signals (TL_FSYNC and TL_MSYNC) supplied by the framer to per- form a parallel-to-serial conversion on the outgoing data that it reads from a multiframe buffer in the order in which it is needed. A rising edge on TL_FSYNC indicates the beginning of a frame, and a rising edge on TL_ MSYNC indicates the beginning of a multiframe. The RFTC realigns when an edge is seen on these signals. It is not necessary to provide an edge every frame or multiframe. Signaling data is driven for all frames of any multiframe and will change only on multiframe boundaries. For T1 mode, signaling data may change every 24th frame. For E1 mode, signaling may change every 16th frame. A special case of E1 mode exists that permits the use of T1 signaling with E1 framing. Normally an E1 multiframe consists of 16 frames of 32 timeslots, where signaling changes on multiframe boundaries. When E1_WITH_T1_SIG is set in LIN_STR_MODE and the line is in E1 mode, the TFTC will use a multiframe consisting of 24 frames in 32 timeslots. In this mode, the AAL1gator II reads signaling on the 24th frame of the multiframe. The signaling nibble is valid for each channel when the last nibble of each channel’s data is being driven. See Figure 48 for an example of signaling bits in a T1 frame. See Figure 49 for an exam- ple of signaling bits in the E1 mode. NOTE: The AAL1gator II treats all 32 timeslots identically. Although E1 data streams con- tain 30 timeslots of channel data and 2 timeslots of control (timeslots 0 and 16), data Figure 48. Output of T1 Signaling Bits Figure 49. Output of E1 Signaling Bits Channel 0 ABCD XXXX Channel 1 ABCD XXXX Channel 2 ABCD Channel 21 ABCD XXXX ABCD Channel 22 Channel 23 ABCD ... ... ... Line Output Signals During Every Frame 0 1 2 21 22 23 XXXX - indicates signaling is invalid XXXX XXXX XXXX TL_SER (timeslots) TL_SIG Channel 0 ABCD XXXX Channel 1 ABCD XXXX Channel 2 ABCD Channel 29 ABCD XXXX ABCD Channel 30 Channel 31 ABCD ... ... ... 0 1 2 29 30 31 XXXX - indicates signaling is invalid XXXX XXXX XXXX TL_SER (timeslots) TL_SIG Line Output Signals During Every Frame |
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