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PM73121 Datasheet(PDF) 92 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 92 Page - PMC-Sierra, Inc |
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92 / 223 page  PM73121 AAL1gator II PMC-Sierra, Inc. PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ To operate at the specified maximum SYS_CLK rate of 38.88 MHz, the external buffers must be of the Fast CMOS TTL (FCT) or Fast (F) family, or of comparable speed. These outputs must be supplied directly to the external devices and no buffering of the signals is allowed. Refer to Figure 108 on page 195 for an example of how to interface memory to the AAL1gator II. Also refer to Table 26 on page 195 for recommended timing parameters. The microprocessor accesses the device by means of the /PROC_CS, /PROC_RD, and /PROC_ WR lines. To perform a write cycle, the /PROC_CS and /PROC_WR lines are asserted. The AAL1gator II then enables the address and data lines at the proper moments and, when complete, the device signals the microprocessor with the /PROC_ACK line. To perform a read, the micro- processor asserts /PROC_CS and /PROC_RD and waits for /PROC_ACK before reading the data. To prevent the microprocessor from obtaining too many memory cycles and interfering with nor- mal AAL1gator II activity, a holdoff circuit is used. This circuit denies the microprocessor an additional access until 20 SYS_CLK cycles have expired since the last microprocessor access. The HOLDOFF output is asserted whenever this denial period is in effect. The microprocessor can poll this output to determine when it will be allowed an access that is not subjected to HOLD- OFF. See timing diagrams starting with Figure 55 on page 92. Refer to section 8 “Application Notes” starting on page 168 for a block diagram of the interface. 3.9 Configuration To transfer TDM data into cells or to transfer cells into TDM data, the PM73121 and each line needs to be configured, and the queues need to be configured and added to determine how the data should be mapped. To configure the AAL1gator II and each line, initialize the COMP_LIN_REG and the LIN_STR_ MODE register for each line. To have these values take affect, the CMD_ATTN bit must be set and the SW_RESET bit in the CMDREG must be cleared. Since no queues are defined at this time, all timeslots in the R_CH_TD_QUEUE_TBL should be initialized to play out conditioned data and the R_COND_DATA field for each timeslot should be initialized to the desired play out value. If signaling is used, then R_COND_SIG should also be initialized. Once the line is configured, queues can be added as described in section 7.11 “Activating a New Queue on an Active Line” on page 167. |
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