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PM73121 Datasheet(PDF) 4 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 4 Page - PMC-Sierra, Inc |
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4 / 223 page  PMC-Sierra, Inc. PM73121 AAL1gator II PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ Issue 1 Issue 2 • Removed Pin 237, P_OUT, from Pinout Table. • In T_QUEUE_TBL, added clarifications to QUEUE_CREDITS and AVG_SUB_VALU fields for single DS0 no pointer mode. • Changed ItypE3 to ItypDS3 in DC Operating Conditions Table. • Changed the following timing parameters: • Interrupt Timing: PROC_INTR Tq(max) from 16 ns to 16.5 ns. • Microprocessor RAM Read Cycle: /MEM_CS Tq(max) from 15 ns to 17.7 ns. • Microprocessor RAM Read Cycle: Tqmoe(max) from 22 ns to 24.7 ns. • Tzsu, Tded, and Tzen are now specified as typical, instead of minimum and maximum. • Microprocessor RAM Write Cycle: /PROC_ACK Tq(max) from 15 ns to 17.5 ns. • Microprocessor RAM Write Cycle: /MEM_CS Tq(max) from 15 ns to 17.7 ns. • Microprocessor Write Command Register: /PROC_ACK Tq(max) from 15 to 17.5 ns. • RAM Write Cycle: /MEM_WE Twp(min) from Tch - 1 to Tch - 1.3, and Twp(max) from Tch to Tch +0.3. • Receive Side Low Speed Interface: TL_SER, TL_SIG Tq(max) from 12 ns to 14 ns. • Transmit Side Interface: RL_SER Th(min) from 1.0 to 1.2 ns. • Transmit Side High-Speed Interface: RL_SER Th(min) from 1.0 to 1.2 ns. • Transmit UTOPIA ATM Timing: TATM_DATA Tq(max) from 12 ns to 12.7 ns. • TUTOPIA SPHY Timing: RPHY_DATA Tq(max) from 12 ns to 12.7 ns. • TUTOPIA MPHY Timing: RPHY_DATA Tq(max) from 12 ns to 12.7 ns. • Added DC Operating Conditions: I TYPE1(max)=420mA and I TYPDS3(max)=482mA. • In Absolute Maximum Ratings section, removed undershoot/ overshoot specification, and replaced with absolute maximum voltage range for TTL inputs. • Moved all timing requirements on external logic for RAM and Microprocessor interface from section 6.5 to section 8.11. From Version To Version Major Changes |
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