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PM73121 Datasheet(PDF) 91 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 91 Page - PMC-Sierra, Inc |
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91 / 223 page  PM73121 AAL1gator II PMC-Sierra, Inc. PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ Adaptive clocking, in general, is not well-suited for voice applications since low frequency or DC changes of the CDV will pass through most filters and cause frame slips. The mechanism shown in Figure 52 can be enhanced for voice applications by adding a low pass filter with a time con- stant greater than the CDV, along with a fine-granularity frequency synthesizer. 3.8 Memory Interface and Arbitration Controller (MIAC) The MIAC is the central arbiter for all memory accesses. It provides a priority mechanism that incorporates fairness to satisfy all real-time requirements of the various blocks. All blocks requesting a data transfer with the common memory supply the address, control signals, and the data, if the requested data transfer is a write, to the MIAC. When the MIAC actually grants the transfer, it provides a grant signal to the requesting block, indicating that the transfer has been performed. The memory is arbitrated on a cycle-by-cycle basis. No device is granted the bus for an indefinite time. The AAL1gator II requires external memory address buffers and data transceivers. The MIAC provides control signals and transceiver enables when a microprocessor cycle is to be performed. The device can directly control external 646-type registered transceivers on the data bus between the memory data interface and the microprocessor’s data bus. The SP_DATA_CLK signal con- trols the writing of data from the memory into the 646 transceiver. The SP_DATA_DIR signal and SP_DATA_EN signal should be used to direct the data through the 646s devices properly. The /SP_ADD_EN signal should be used as a tristate enable for the external address buffers. The AAL1gator II controls the tristating of its own address and data bus drivers so no conflicts occur with the microprocessor external buffers. Figure 52. Direct Adaptive Clock Operation Channel Status AAL1 SAR Processor (AAL1gator II) TL_CLK TL_SER TL_SIG Framer Line Interface with Transmit Jitter Attenuator Gain Frequency Synthesizer Use Nominal Frequency Frame Difference Nominal Frame Difference Underrun |
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