PM7341 datasheet(112/413 Pages) PMC

112 / 413 page

PRELIMINARY

INVERSE MULTIPLEXING OVER ATM

PM7341 S/UNI-IMA-84

DATASHEET

PMC-2000223

ISSUE 4

INVERSE MULTIPLEXING OVER ATM

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

114

Figure 23

- 8 MByte

SYSCLK

CBCSB

CBRASB

CBCASB

CBWEB

CBBS[1:0]

CBA[11:0]

CBDQM

CBDQ[15:0]

CKE

CLK

Addr/Ctrl

DQM

DQ[15:0]

4 x 4k x 256 x 16

clock source

There are three processes, all of which are arbitrated by the SDRAM arbiter, that

access the cell buffer SDRAM:

1. The RDAT, which reads and writes cell and status information. The granularity

of access by the RDAT is a concatenated 1-cell write, 1-cell read. Either the

write or the read may not be performed, depending on the RDATs

requirements.

2. The microprocessor interface, which performs diagnostic reading or writing of

64 bytes of data. This data is aligned with the cell data. This access is allowed

only when the SDRAM is placed in Diagnostic mode and is provided both to

enable SDRAM testing and to initialize the SDRAM. While it is in diagnostic

mode, all regular accesses from the RDAT are disabled

3. The refresh controller, which has a programmable refresh rate.

The SDRAM interface will perform the initialization sequence for the SDRAM.

This sequence is triggered by the SDRAM enable bit in the SDRAM control

sequential access, write burst mode, and a burst length of 8. Applications should

ensure that sufficient time is provided between SDRAM power up and when this

enable bit is set.

PM7341 Datasheet(PDF) 112 Page - PMC-Sierra, Inc

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