PM7375-SC datasheet(189/430 Pages) PMC

189 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

173

Zero Common Part Indicator Errors register has incremented since the last

accumulation interval.

RCRC10_CH:

When logic one, the RCRC10_CH bit indicates that the SAR PMON Receive

CRC-10 Errors register has incremented since the last accumulation interval.

RUVPI/VCI_CH:

When logic one, the RUVPI/VCI_CH bit indicates that the SAR PMON Receive

Unprovisioned VPI/VCI Errors register has incremented since the last

accumulation interval.

OVR:

The overrun (OVR) bit indicates the overrun status of the SAR PMON Holding

Registers. A logic one in this bit position indicates that a previous interrupt has

not been cleared before the end of the next accumulation interval, and that the

contents of the Holding Registers have been overwritten. A logic zero indicates

that no overrun has occurred. This bit is reset to logic zero when this register is

read.

INTR:

The interrupt (INTR) bit indicates the current status of the internal interrupt

signal. A logic one in this bit position indicates that a transfer of counter values

to the SAR PMON Holding Registers has occurred; a logic zero indicates that no

transfer has occurred. This bit is set to logic zero when this register is read. The

value of the INTR bit is not affected by the value of the INTE bit.

INTE:

The interrupt enable (INTE) bit controls the operation of the appropriate interrupt

output. A logic one in the INTE bit position enables the SAR PMON to generate

a microprocessor interrupt when the counter values are transferred to the SAR

PMON Holding Registers. A logic zero in the INTE bit position disables the SAR

PMON from generating an interrupt. When the SAR PMON is reset, the INTE bit

is set to logic zero, disabling the interrupt. The interrupt is cleared when this

PM7375-SC Datasheet(PDF) 189 Page - PMC-Sierra, Inc