PM7375-SC datasheet(126/430 Pages) PMC

126 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

110

Bit 2

TRCLKA

Bit 1

RCLKA

Bit 0

TCLKA

This register provides activity monitoring on LASAR-155 clocks. When a monitored

clock signal makes a low to high transition, the corresponding register bit is set high.

The bit will remain high until this register is read, at which point, all the bits in this

bit reading low. This register should be read at regular intervals to detect clock

failures.

TCLKA:

The TCLK active (TCLKA) bit monitors for low to high transitions on the TCLK

output. TCLKA is set high on a rising edge of TCLK, and is set low when this

RCLKA:

The RCLK active (RCLKA) bit monitors for low to high transitions on the RCLK

output. RCLKA is set high on a rising edge of RCLK, and is set low when this

TRCLKA:

The TRCLK active (TRCLKA) bit monitors for low to high transitions on the

TRCLK+ and TRCLK- inputs. TRCLKA is set high on a rising edge of TRCLK+,

and is set low when this register is read.

RRCLKA:

The RRCLK active (RRCLKA) bit monitors for low to high transitions on the

RRCLK+ and RRCLK- inputs. RRCLKA is set high on a rising edge of RRCLK+,

and is set low when this register is read.

PCICLKA:

The PCICLK active (PCICLKA) bit monitors for low to high transitions on the

PCICLK input. PCICLKA is set high on a rising edge of PCICLK, and is set low

when this register is read.

SYSCLKA:

The SYSCLK active (SYSCLKA) bit monitors for low to high transitions on the

SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set

low when this register is read.

PM7375-SC Datasheet(PDF) 126 Page - PMC-Sierra, Inc