| Electronic Components Datasheet Search |
|
PM7375-SC Datasheet(PDF) 128 Page - PMC-Sierra, Inc |
|
|
|||||||||||||||||||||||||||||
PM7375-SC Datasheet(HTML) 128 Page - PMC-Sierra, Inc |
|
128 / 430 page ![]() PM7375 LASAR-155 DATA SHEET PMC-931127 ISSUE 6 LOCAL ATM SAR & PHYSICAL LAYER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 112 LOOPT: The LOOPT bit selects the source of timing for the transmit section of the LASAR-155. When LOOPT is a logic zero, the transmitter timing is derived from inputs TRCLK+ and TRCLK-. When LOOPT is a logic one, the transmitter timing is derived from the receiver inputs RXD+ and RXD- when clock recovery is enabled and from RRCLK+ and RRCLK- when clock recovery is disabled. DLE: The DLE bit enables the LASAR-155 diagnostic loopback. When DLE is a logic one, the transmit stream is connected to the receive stream. Note, whether loopback is through the CRU or not depends on the RBYP bit in the LASAR-155 Master Configuration register. Simultaneous diagnostic loopback and line loopback is not supported. LLE: The LLE bit enables the LASAR-155 line loopback. When LLE is a logic one, RXD+ and RXD-, are connected internally to TXD+ and TXD-, respectively. Simultaneous diagnostic loopback and line loopback is not supported. Polarity invert (RXDINV) is not supported when line loopback (LLE) is enabled (If LLE = 1 then RXDINV must be set to 0). FIXPTR: The FIXPTR bit disables transmit payload pointer adjustments. If the FIXPTR bit is a logic 1, the transmit payload pointer is set at 522. If FIXPTR is a logic zero, the payload pointer is controlled by the contents of the TPOP Pointer Control register. LCDV: The LCDV bit reflects the current loss of cell delineation state. LCDV becomes a logic 1 when an out of cell delineation state has persisted for 4 ms without any lower level alarms (LOS, LOP, Path AIS, Line AIS) occurring. LCDV becomes logic 0 when the SYNC state has been maintained for 4 ms. LCDE: The LCDE bit enables the loss of cell delineation (LCD) interrupt. When logic one, the LASAR-155 INTB or PCIINTB output is asserted when there is a change in the LCD state. When logic zero, the LASAR-155 INTB or PCIINTB output is not affected by the change in LCD state. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |